关键词: 仿真, 晶圆级芯片封装, 芯片应力, 重布线层, 顶层金属

Abstract: Wafer-level chip-scale packaging (WLCSP) leverages redistribution layer (RDL) to markedly increase the I/O density, making it a key technology for achieving high-density, high-performance packaging. During service, WLCSP devices experience pronounced temperature excursions. The mismatch in coefficients of thermal expansion (CTE) among dissimilar materials induces delamination, cracking, and ultimately packaging interconnection failure. The root cause of chip interconnect failure is excessive stress, and variations in the top-metal (TM) layer can significantly affect the magnitude of this stress. Based on this failure issue, the impact of the degree and location of sparsity in both the RDL and TM, RDL continuity, and chip structure stress in WLCSP structures is systematically investigated, and a systematic summary of chip failure issues in WLCSP structures and recommendations for optimization are provided. The results indicate that the non-uniform distributions of RDL and TM in 1P2M have a significant impact on stress, the precise sparse location within each layer has limited impact, the better the RDL continuity, the lower the stress, the larger the sparse area of the TM, the higher the stress. Compared to the 1P2M structure, the 2P2M structure significantly reduces chip stress, non-uniform TM distribution has little effect on chip stress, whereas non-uniform RDL distribution has a significant impact on chip stress.

Key words: simulation, WLCSP, chip stress, RDL, top-metal