集成电路三维封装力学仿真方法综述*

doi:10.16257/j.cnki.1681-1070.2026.0108

电子与封装 ›› 2026, Vol. 26 ›› Issue (3): 030009 . doi: 10.16257/j.cnki.1681-1070.2026.0108

• “电子封装力学仿真方法进展及应用”专题 • 上一篇下一篇

集成电路三维封装力学仿真方法综述^*

王凤娟¹，马丁¹，孙传鸿¹，尹湘坤²，杨媛¹，余宁梅¹，余明斌¹，李言^1,3

1. 西安理工大学光子功率器件与放电调控陕西省高等学校重点实验室，西安 710048；2. 西安电子科技大学集成电路学院模拟集成电路与系统教育部重点实验室，西安 710071；3. 新疆工程学院，乌鲁木齐 830023

收稿日期:2025-11-18 出版日期:2026-04-02 发布日期:2026-04-02
作者简介:王凤娟（1985—），女，河北衡水人，教授，主要研究方向为基于硅通孔的集成无源器件设计、三维集成电路热管理及其热机械特性、寄生参数提取等。

Review of Mechanical Simulation Methods for 3D Integrated Circuit Packaging

WANG Fengjuan¹, MA Ding¹, SUN Chuanhong¹, YIN Xiangkun², YANG Yuan¹, YU Ningmei¹, YU Mingbin¹, LI Yan^1,3

1. The Key Laboratory of Photonic Power Devices andDischarge Regulation in Shaanxi Province's Institutions of HigherEducation, Xi'anUniversity of Technology, Xi'an710048, China; 2.The Key Laboratory of AnalogIntegrated Circuits and Systems Ministry of Education,School of Integrated Circuits, Xidian University,Xi'an 710071, China; 3. Xinjiang Institute ofEngineering, Urumqi 830023, China

Received:2025-11-18 Online:2026-04-02 Published:2026-04-02

摘要/Abstract

摘要： 随着芯片集成度的不断提升与封装尺寸的持续缩小，摩尔定律逐渐逼近物理极限。为延续摩尔定律的发展，传统的二维平面封装已逐步向三维立体封装演进。然而，由于三维（3D）封装的复杂性和异构性，且封装结构内部不同材料的热膨胀系数（CTE）存在差异，在温度循环、工作高温及环境应力的共同作用下，界面处易产生热应力集中，进而引发焊点疲劳断裂、硅通孔（TSV）侧壁开裂及层间剥离等力学失效问题。在此背景下，3D封装力学仿真技术已成为解决此类问题的重要手段，开展相关研究的必要性与紧迫性日益突出。系统梳理集成电路3D封装力学仿真技术的现有研究方法与最新进展，明确3D封装典型力学失效问题及对应的力学本构与失效准则，分类阐述有限元法（FEM）、边界元法（BEM）2类核心仿真方法的基本原理、适用场景及技术局限，进而分析基于FEM和BEM的多物理场耦合仿真方法的技术演进逻辑及其在复杂失效场景中的应用价值，总结当前技术体系的核心瓶颈，并展望其未来发展前景。

关键词: 三维集成电路封装, 有限元法, 边界元法, 多物理场耦合仿真

Abstract: With the continuous increase in chip integration and the ongoing reduction in packaging size, Moore's Law is gradually approaching its physical limits. To continue the development of Moore's Law, traditional two-dimensional planar packaging is gradually evolved towards three-dimensional (3D) packaging. However, due to the complexity and heterogeneity of 3D packaging, as well as differences in the coefficients of thermal expansion (CTE) of different materials within the packaging structure, thermal stress concentrations tend to occur at interfaces under the combined effects of temperature cycling, high operating temperatures, and environmental stress. This can lead to mechanical failures such as solder joint fatigue fracture, through-silicon via (TSV) sidewall cracking, and interlayer delamination. Against this backdrop, 3D packaging mechanical simulation technology is recognized as an important means of solving such problems, and the necessity and urgency of related research are increasingly prominent. The existing research methods and latest advancements in mechanical simulation technology for 3D integrated circuit packaging are systematically reviewed. The typical mechanical failure modes of 3D packaging and the corresponding mechanical constitutive models and failure criteria are clarified. The basic principles, applicable scenarios, and technical limitations of the two core simulation methods, namely the finite element method (FEM) and the boundary element method (BEM), are classified and elaborated. Furthermore, the technological evolution logic of multiphysics coupling simulation methods based on FEM and BEM, as well as their application value in complex failure scenarios, are analyzed. The core bottlenecks of the current technical system are summarized, and its future development prospects are prospected.

Key words: three-dimensional integrated circuit packaging, finite element method, boundary element method, multi-physics coupling simulation

中图分类号:

王凤娟, 马丁, 孙传鸿, 尹湘坤, 杨媛, 余宁梅, 余明斌, 李言. 集成电路三维封装力学仿真方法综述^*[J]. 电子与封装, 2026, 26(3): 030009 .

WANG Fengjuan, MA Ding, SUN Chuanhong, YIN Xiangkun, YANG Yuan, YU Ningmei, YU Mingbin, LI Yan. Review of Mechanical Simulation Methods for 3D Integrated Circuit Packaging[J]. Electronics & Packaging, 2026, 26(3): 030009 .

参考文献

[1] LAU J H. Recent advances and trends in advanced packaging[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2022, 12(2): 228-252.
[2] SHIH M K, LAI W H, LIAO T, et al. Thermal and mechanical characterization of 2.5-D and fan-out chip on substrate chip-first and chip-last packages[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2022, 12(2): 297-305.
[3] OZKAN M, POMPA L, BIN IQBAL M S, et al. Performance, efficiency, and cost analysis of wafer-scale AI accelerators vs. single-chip GPUs[J]. Device, 2025, 3(10): 100834.
[4] HAN Y H, XU H B, LU M X, et al. The big chip: challenge, model and architecture[J]. Fundamental Research, 2023, 4(6): 1431-1441.
[5] MA A W, GAO B, LU Y Y, et al. Multi-scale thermal modeling of 3D-heterogeneous integrated processing-near-memory chip for edge large language model inference[C]// 2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Hong Kong, China, 2025: 1-3.
[6] WANG S X, YU S X, CHEN W T, et al. Study on microfluidic heat dissipation enhancement and thermal stress analysis in three-dimensional integrated circuit with through silicon via structures[J]. Applied Thermal Engineering, 2025, 279: 127699.
[7] BOJITA A, PURCAR M, SIMON D, et al. A novel multi-scale method for thermo-mechanical simulation of power integrated circuits[J]. IEEE Journal of the Electron Devices Society, 2022, 10: 169-179.
[8] QU W Z, ZHANG Y M, GU Y, et al. Three-dimensional thermal stress analysis using the indirect BEM in conjunction with the radial integration method[J]. Advances in Engineering Software, 2017, 112: 147-153.
[9] TIAN L, LIU Y Z, CHEN W C. Multiphysics simulation of chiplet integration process-induced stress effects on AC and DC quantum transport of FinFET from system technology co-optimization perspective[J]. IEEE Transactions on Electron Devices, 2024, 71(12): 7294-7301.
[10] MA X N, XU Q Z, WANG C H, et al. An electrical-thermal co-simulation model of chiplet heterogeneous integration systems[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024, 32(10): 1769-1781.
[11] 萧金庆, 李军辉. 基于有限元模拟的三维集成微系统热循环可靠性研究[J]. 导航与控制, 2022, 21(3): 174-180.
[12] LIU Y, YAO C, SUN F L, et al. Numerical simulation of reliability of 2.5D/3D package interconnect structure under temperature cyclic load[J]. Microelectronics Reliability, 2021, 125: 114343.
[13] XU X, LIU Y, SU Y H, et al. Fatigue behavior of 3D stacked packaging structures under extreme thermal cycling condition[J]. Memories - Materials, Devices, Circuits and Systems, 2023, 4: 100032.
[14] LU K H, ZHANG X F, RYU S K, et al. Thermo-mechanical reliability of 3-D ICs containing through silicon vias[C]// 2009 59th Electronic Components and Technology Conference, San Diego, CA, 2009: 630-634.
[15] RYU S K, LU K H, ZHANG X F, et al. Impact of near-surface thermal stresses on interfacial reliability of through-silicon vias for 3-D interconnects[J]. IEEE Transactions on Device and Materials Reliability, 2011, 11(1): 35-43.
[16] LEE S C, HAN S W, HONG J P, et al. Novel method of wafer-level and package-level process simulation for warpage optimization of 2.5D TSV[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2021: 1527-1531.
[17] PANIGRAHY S K, FA X C, ONG Y C, et al. Integration of artificial neural network and finite element simulation for package warpage prediction[C]// 2023 IEEE 25th Electronics Packaging Technology Conference (EPTC), Singapore, 2024: 926-931.
[18] CHEN K S, WU W C. Data-driven stress/warpage analyses based on stoney equation for packaging applications[J]. IEEE Transactions on Device and Materials Reliability, 2024, 24(1): 112-122.
[19] XIAO M T, YANG B G, ZHANG Q, et al. Failure mechanisms and predictive modeling of micro solder joints under thermal cycling[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2025, 15(12): 2638-2644.
[20] JIANG L L, ZHU W H, HE H. Comparison of darveaux model and coffin-manson model for fatigue life prediction of BGA solder joints[C]// 2017 18th International Conference on Electronic Packaging Technology (ICEPT), Harbin, China, 2017: 1474-1477.
[21] LIU L, WANG F J, YIN X K, et al. Optimization of 3-D IC routing based on thermal equalization analysis[J]. IEEE Transactions on Device and Materials Reliability, 2024, 24(2): 250-259.
[22] YIN X K, LI X, QIAN L B, et al. Numerical analysis and optimization of chip-level drop impact reliability for chiplet based on Si interposer[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2025, 15(6): 1203-1212.
[23] LAU C S, YE N, TAKIAR H. Realistic solder joint geometry integration with finite element analysis for reliability evaluation of printed circuit board assembly[C]// 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA, 2019: 1387-1395.
[24] HAN M S, SHIN Y, LIM K, et al. A development of finite element analysis model of 3D IC TSV package warpage considering cure dependent viscoelasticity with heat generation[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2021: 1475-1480.
[25] CHEN Z W, ZHANG Z, DONG F, et al. A hybrid finite element modeling: artificial neural network approach for predicting solder joint fatigue life in wafer-level chip scale packages[J]. Journal of Electronic Packaging, 2021, 143: 011001.
[26] YUAN C C A, LEE C C. Solder joint reliability modeling by sequential artificial neural network for glass wafer level chip scale package[J]. IEEE Access, 2020, 8: 143494-143501.
[27] HE Y D, GONG Y P, XU H, et al. A FEM-BEM coupling scheme for elastic dynamics problems in electronic packaging[C]// 2024 25th International Conference on Electronic Packaging Technology (ICEPT), Tianjin, China, 2024: 1-5.
[28] WANG Y, ZHANG T, FENG C L, et al. Multiphysics coupling analysis and structural optimization of high density TSVs in microsystems[C]// 2022 23rd International Conference on Electronic Packaging Technology (ICEPT), Dalian, China, 2022: 1-6.
[29] HE W, WANG Z X, LI J Q, et al. Investigation of heat transfer performance for through-silicon via embedded in micro pin fins in 3D integrated chips[J]. International Journal of Heat and Mass Transfer, 2023, 214: 124442.
[30] WU X P, CAO M P, SHAN G B, et al. A fast analysis method of multiphysics coupling for 3-D microsystem[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 41(8): 2372-2379.
[31] WANG J P, ZHANG J, WANG L L, et al. An novel evaluation methodology for EV-SiC power module considering operation condition and multiphysics coupling effects[C]// 2021 IEEE 12th Energy Conversion Congress & Exposition - Asia (ECCE-Asia), Singapore, 2021: 1593-1598.

中国电子学会电子制造与封装技术分会会刊

中国半导体行业协会封测分会会刊

无锡市集成电路学会会刊

集成电路三维封装力学仿真方法综述^*

Review of Mechanical Simulation Methods for 3D Integrated Circuit Packaging

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 3

编辑推荐

Metrics

本文评价

[1]	高方腾, 陈沛, 杨茗勋, 秦飞. 基于边的光滑有限元法的封装模块电热力仿真研究^*[J]. 电子与封装, 2026, 26(3): 30005-.
[2]	李杰，曹世博，余伟，李泽源，乔志壮，刘林杰，张召富，刘胜，郭宇铮. 基于试验与仿真的CBGA焊点寿命预测技术^*[J]. 电子与封装, 2025, 25(7): 70201-.
[3]	韩星，梁若男，谢达，郭俊杰. IMC厚度对大尺寸高密度电路可靠性的影响[J]. 电子与封装, 2025, 25(10): 100203-.