关键词: 仿真, WLCSP, 芯片应力, RDL, Top metal

Abstract: Wafer-level chip-scale packaging (WLCSP) leverages redistribution layer (RDL) technology to markedly increase the number of I/Os per unit area, making it a key enabler for high-density, high-performance packages. During service, WLCSP devices experience pronounced temperature excursions; the mismatch in coefficients of thermal expansion (CTE) among dissimilar materials induces delamination, cracking, and ultimately interconnection failure. The root cause of these failures is excessive stress, which is strongly influenced by the non-uniformity of the top-metal layer in the RDL stack. Motivated by this reliability challenge, we systematically investigated how the degree and location of sparsity in both the RDL and top metal, RDL continuity, and overall package architecture affect on-chip stress. The study culminates in generalized design rules and optimization guidelines for mitigating chip-level failures in WLCSP. Key findings are as follows: In the 1P2M configuration, non-uniform distributions of both RDL and top metal significantly elevate stress; however, the precise sparse location within each layer has limited impact. Greater RDL continuity reduces stress, whereas larger top-metal sparse areas increase stress. Transitioning from 1P1M to 2P2M markedly lowers overall chip stress. In the 2P2M architecture, non-uniform top-metal patterns exert negligible influence on stress, while RDL non-uniformity remains a dominant factor.

Key words: simulation, WLCSP, chip stress, RDL, top metal