关键词: FPGA, 可测性设计, 开关矩阵, PCIe, Tessent

Abstract: In recent years, the design and manufacturing technology of field programmable gate array (FPGA) has developed rapidly, and FPGA testing has also become an important issue. Efficient testability design solution plays a decisive role in reducing test costs, improving test coverage and test efficiency. With the combination of FPGA switch matrix structure and design for test (DFT) technology, an intellectual property (IP) core efficient test scheme for FPGA custom circuits is realized. Its effectiveness and achievability are demonstrated by automatic test equipment (ATE). This design example is based on peripheral component interconnect express (PCIe). In the traditional DFT process, a new programmable and efficient testability design is evolved in combination with the characteristic of the FPGA architecture.

Key words: FPGA, testabilitydesign, switchmatrix, PCIe, Tessent