关键词: 矩阵计算, 异构, 硬件加速器, 算子映射

Abstract: A general-purpose central processing unit (CPU) usually spends most resources on cache management and logic control, and only a small portion of its resources on computation.Therefore, it has become a trend to design a heterogeneous multi-core system with dedicated computing modules such as graphics processing unit (GPU), digital signal processor (DSP), FPGA and other programmable logic units, to enhance the computation performance. Based on this trend, an acceleration system for matrix computation is proposed with self-developed special instruction set, specially designed hardware accelerator array and optimization in storage architecture, to speed up matrix computing operations.In addition, communication operations with other systems after heterogeneous integration are realized through the mailbox mechanism.A performance verification platform is built through Python and UVM verification methodology to carry out the register transfer level (RTL) performance verification.The results show that the operational performance of the subsystems in the scheme can reach up to 32 GFLOPS at 500 MHz operating frequency, and the computational efficiency of the general matrix multiplication (GEMM) operator is improved by 12 times compared to the coprocessor scheme that performs acceleration using a 2D pulsating array alone.

Key words: matrix computation, heterogeneous, hardware accelerator, operator mapping