中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2026, Vol. 26 ›› Issue (1): 010403 . doi: 10.16257/j.cnki.1681-1070.2026.0007

• 材料、器件与工艺 • 上一篇    下一篇

重掺衬底硅外延过程中失配位错对几何参数影响研究

马梦杰,王银海,邓雪华,尤晓杰   

  1. 南京国盛电子有限公司,南京  211111
  • 收稿日期:2025-05-26 出版日期:2026-01-29 发布日期:2025-06-27
  • 作者简介:马梦杰(1987—),男,河南驻马店人,硕士,高级工程师,主要研究方向为半导体材料外延。

Study on the Impact of Misfit Dislocations on Geometric Parameters During Silicon Epitaxy on Heavily Doped Substrate

MA Mengjie, WANG Yinhai, DENG Xuehua, YOU Xiaojie   

  1. Nanjing Guosheng Electronics Co., Ltd., Nanjing 211111, China
  • Received:2025-05-26 Online:2026-01-29 Published:2025-06-27

摘要: 重掺磷衬底上生长高阻外延层时,由于衬底和外延层之间存在晶格失配和热膨胀系数失配,随着外延生长,外延层超过临界厚度时会产生失配位错来释放应力,失配位错会向外扩展,不仅严重影响了外延材料的电性能和可靠性,也导致外延片几何参数变差。采用Surfscan SP1表面缺陷检测仪量化表征了外延层失配位错密度,通过调节外延生长速率实现对失配位错密度的控制,分析了失配位错密度对外延几何参数的影响。随着失配位错密度的增加,翘曲度从65 μm增加至90 μm、弯曲度从31 μm增加至42 μm。

关键词: 硅外延, 重掺磷衬底, 失配位错, 几何参数

Abstract: When growing high-resistivity epitaxial layers on heavily phosphorus-doped substrates, lattice mismatch and thermal expansion coefficient mismatch between the substrate and epitaxial layer cause misfit dislocations to form as the epitaxial layer exceeds a critical thickness during growth, thereby releasing stress. These misfit dislocations propagate outward, severely compromising the electrical properties and reliability of the epitaxial material while also degrading the geometric parameters of the epitaxial wafer. The misfit dislocation density in the epitaxial layer is quantified using the Surfscan SP1 surface inspection system. By adjusting the epitaxial growth rate, control over the misfit dislocation density is achieved. The impact of misfit dislocation density on epitaxial geometric parameters is analyzed. As the misfit dislocation density increases, warp increases from 65 μm to 90 μm, and bow increases from 31 μm to 42 μm.

Key words: silicon epitaxy, heavily phosphorus-doped substrate, misfit dislocation, geometric parameters

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