14 bit、10 GSample/s数模转换器研究与设计*

doi:10.16257/j.cnki.1681-1070.2025.0140

电子与封装 ›› 2025, Vol. 25 ›› Issue (12): 120301 . doi: 10.16257/j.cnki.1681-1070.2025.0140

14 bit、10 GSample/s数模转换器研究与设计^*

宋新瑶¹，李浩¹，唐天哲¹，张有涛⁴，叶庆国⁴，张翼^1,^2,3

1. 南京邮电大学集成电路科学与工程学院，南京 210023；2. 南京邮电大学射频集成与微组装技术国家地方联合工程实验室，南京 210023；3. 微波毫米波单片集成和模块电路重点实验室，南京 210016；4. 南京国博电子股份有限公司，南京 211153

收稿日期:2025-03-11 出版日期:2025-12-26 发布日期:2025-06-30
作者简介:宋新瑶（2000—），男，江苏徐州人，硕士研究生，主要研究方向为数模混合集成电路设计。

Research and Design of 14-bit and 10 GSample/s DAC

SONG Xinyao¹, LI Hao¹, TANG Tianzhe¹, ZHANG Youtao⁴, YE Qingguo⁴, ZHANG Yi^1,2,3

1. College of Integrated Circuit Science and Engineering, NanjingUniversity of Posts and Telecommunications, Nanjing 210023, China; 2. National and Local Joint Engineering Laboratory of RF Integration andMicro-Assembly Technology, Nanjing University of Posts andTelecommunications, Nanjing 210023, China; 3. Science andTechnology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing 210016, China; 4. Nanjing GuoBo Electronics Co., Ltd.,Nanjing 211153, China

Received:2025-03-11 Online:2025-12-26 Published:2025-06-30

摘要/Abstract

摘要： 基于180 nm SiGe BiCMOS工艺设计了一款14 bit、10 GSample/s的电流舵型超高速高精度数模转换器（DAC）。为提高线性度、降低输出毛刺，电路采用9+5分段式译码，其中低9 bit二进制码由R-2R梯形电阻网络完成加权，高位采用温度计码结构。针对高频下电流源开关因输出阻抗衰减和不平衡导致动态性能下降的问题，通过改进电流源开关的结构，缩小了电流源开关两端的输出阻抗差值，这一改进减小了非线性失真，从而提升了高频无杂散动态范围（SFDR）。由后仿真结果可知，电路功耗为4.96 W，微分非线性为0.58 LSB，积分非线性为0.72 LSB，第一奈奎斯特区内SFDR不低于64[s1] dBc，动态性能良好。

关键词: DAC, SiGeBiCMOS, 无杂散动态范围, 电流舵

Abstract: A 14-bit, 10 GSample/s current-steering ultra-high-speed high-precision digital-to-analog converter (DAC) has been designed based on an 180 nm SiGe BiCMOS process. To improve linearity and reduce output glitches, the circuit employs a 9+5 segmented decoding scheme, where the lower 9 bits of the binary code are weighted using an R-2R ladder resistor network, and the higher-order bits adopt a thermometer code structure. To address the issue of degradation of dynamic performance caused by output impedance attenuation and imbalance in current source switches at high frequencies, the switch structure is optimized to effectively reduce the output impedance mismatch across the current switch. This structural improvement significantly minimizes nonlinear distortion, thereby improving the high-frequency spurious-free dynamic range (SFDR). The post-simulation results show that the circuit power consumption is 4.96 W, with a differential nonlinearity of 0.58 LSB and an integral nonlinearity of 0.72 LSB. The SFDR within the first Nyquist zone is no less than 64.36 dBc, indicating good dynamic performance.

Key words: DAC, SiGe BiCMOS, spurious-free dynamic range, current steering

中图分类号:

TN402

宋新瑶，李浩，唐天哲，张有涛，叶庆国，张翼. 14 bit、10 GSample/s数模转换器研究与设计^*[J]. 电子与封装, 2025, 25(12): 120301 .

SONG Xinyao, LI Hao, TANG Tianzhe, ZHANG Youtao, YE Qingguo, ZHANG Yi. Research and Design of 14-bit and 10 GSample/s DAC[J]. Electronics & Packaging, 2025, 25(12): 120301 .

参考文献

[1] MITROVIC I Z, BUIU O, HALL S, et al. Review of SiGe HBTs on SOI [J]. Solid-State Electronics, 2005, 49(9): 1556-1567.
[2] ZHOU L, LI W Z, WU D Y, et al. A 30 GSps 6 bit DAC in SiGe BiCMOS technology[C]//2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), Monte Carlo, Monaco, 2017: 37-40.
[3] MOENECLAEY B, VERPLAETSE M, RAMON H, et al. A 6-bit 56-GSa/s DAC in 55 nm SiGe BiCMOS[C]//2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), Monterey, CA, USA, 2022: 1-4.
[4] POULTON K, JEWETT B, LIU J. A 7.2-GSa/s, 14-bit or 12-GSa/s, 12-bit DAC in a 165-GHz fT BiCMOS process[C]//2011 Symposium on VLSI Circuits - Digest of Technical Papers, Kyoto, Japan, 2011: 62-63.
[5] DUNCAN L, DUPAIX B, MCCUE J J, et al. A 10-bit DC-20-GHz multiple-return-to-zero DAC with >48-dB SFDR[J]. IEEE Journal of Solid-State Circuits, 2017, 52(12): 3262-3275.
[6] ZHOU L, WU D Y, JIANG F, et al. A 2GSps 12bit DAC with SFDR >57.5dBc up to Nyquist bandwidth[C]//2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), Bordeaux, France, 2014: 219-222.
[7] 薛晓博. 高速高精度电流舵数模转换器关键设计技术的研究与实现[D]. 杭州: 浙江大学, 2014.
[8] 张翼, 戚骞, 张有涛, 等. 基于0.18 μm SiGe BiCMOS工艺的4 GS/s、14 bit数模转换器[J]. 南京邮电大学学报(自然科学版), 2024, 44(3): 42-47.
[9] 桂伯正, 黄嵩人. 一种12位电压与电流组合型DAC设计[J]. 电子与封装, 2025, 25(2): 020301.
[10] LUSCHAS S, LEE H S. Output impedance requirements for DACs[C]//Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03, Bangkok, Thailand, 2003.
[11] VAN DEN BOSCH A, STEYAERT M, SANSEN W. SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters[C]//ICECS'99. Proceedings of ICECS '99.6th IEEE International Conference on Electronics, Circuits and Systems, Paphos, Cyprus, 2002: 1193-1196.
[12] AHMAD T, REZAZADEH A, Gill S S. Current dependence of small signal base-collector capacitance in microwave AlGaAs/GaAs HBTs[C]//ESSDERC'94: 24th European Solid State Device Research Conference, Edinburgh, UK, 1994: 443-446.
[13] CHEN W L, CHAU H F, TUTT M, et al. High-speed InGaP/GaAs HBTs using a simple collector undercut technique to reduce base-collector capacitance[J]. IEEE Electron Device Letters, 1997, 18(7): 355-357.
[14] 王铭, 张有涛, 叶庆国, 等. 基于InP HBT的SFDR＞63 dB 12位6 GS/s高速数模转换器[J]. 电子技术应用, 2020, 46(4): 34-39.
[15] BULT K, LIN C H, VAN DER GOES F, et al. A 12 b 2.9 GS/s DAC with IM3<–60 dBc Beyond 1 GHz in 65 nm CMOS[M]//Analog Circuit Design. Dordrecht: Springer Netherlands, 2011: 119-136.
[16] 陈宇轩, 季伟伟, 解维坤, 等. 高精度数模转换器的线性度测试技术[J]. 电子与封装, 2023, 23(5): 050202.
[17] HUANG H Y, CHEN X Y, KUO T H. A 10-GS/s NRZ/mixing DAC with switching-glitch compensation achieving SFDR >64/50 dBc over the first/second Nyquist zone[J]. IEEE Journal of Solid-State Circuits, 2021, 56(10): 3145-3156.
[18] ERDMANN C, CULLEN E, BROUARD D, et al. 16.3 A 330 mW 14 b 6.8 GS/s dual-mode RF DAC in 16 nm FinFET achieving ?70.8 dBc ACPR in a 20MHz channel at 5.2 GHz[C]//2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2017: 280-281.
[19] RAVINUTHULA V, BRIGHT W, WEAVER M, et al. A 14-bit 8.9 GS/s RF DAC in 40 nm CMOS achieving >71 dBc LTE ACPR at 2.9 GHz[C]//2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, USA, 2016: 1-2.

中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

14 bit、10 GSample/s数模转换器研究与设计^*

Research and Design of 14-bit and 10 GSample/s DAC

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 8

编辑推荐

Metrics

本文评价

[1]	戴星明;刘颖异;唐旭升. 电流舵数模转换器的静态误差分析与建模^*[J]. 电子与封装, 2022, 22(8): 80303-.
[2]	杨志新;Maureen Willis;高博;龚敏. 13位高无杂散动态范围的SAR ADC[J]. 电子与封装, 2022, 22(12): 120303-.
[3]	康明超;孔祥艺;黄立朝;丁宁;时晨杰. 一种双通道16位串行数模转换器电路设计[J]. 电子与封装, 2021, 21(6): 60301-.
[4]	车来晟，唐鹤，高昂，牛胜普. 一款10位逐次逼近型模数转换器设计[J]. 电子与封装, 2019, 19(7): 16-19.
[5]	郑炯卫，唐　鹤，刘增鑫，陈科全，杨　磊，甄少伟，张　波. 基于双斜坡采样的像素级时间幅度变换器[J]. 电子与封装, 2018, 18(7): 22-27.
[6]	谭　萍，高　博，龚　敏，赵　新，钱　正，王堋钰. 一种12位84 dB无杂散动态范围的高精度低功耗SAR ADC[J]. 电子与封装, 2018, 18(7): 16-21.
[7]	陈钟鹏, 华玲. 一种多通道直接数字频率合成器的设计[J]. 电子与封装, 2018, 18(4): 22-25.
[8]	杨俊浩，张甘英，张　涛. 一种应用于DDS 14位1 GS/s电流舵型DAC的设计[J]. 电子与封装, 2016, 16(8): 30-33.