中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2025, Vol. 25 ›› Issue (12): 120302 . doi: 10.16257/j.cnki.1681-1070.2025.0166

• 电路与系统 • 上一篇    下一篇

一种流水线架构的2D-FFT加速引擎设计

王培富1,李振涛1,2   

  1. 1.长沙理工大学物理与电子科学学院,长沙 410114;2.湖南毂梁微电子有限公司,长沙 410003
  • 收稿日期:2025-08-03 出版日期:2025-12-26 发布日期:2025-08-28
  • 作者简介:王培富(2002—),男,湖南省衡阳市人,硕士研究生,主要研究方向为数字集成电路设计。

Design of a 2D-FFT Acceleration Engine with Pipelined Architecture

WANG Peifu1, LI Zhentao1, 2   

  1. 1.School of Physics and Electronic Science, Changsha University of Science and Technology, Changsha,410114, China; 2.Hunan Guliang Microelectronics Co.,Ltd., Changsha 410003, China
  • Received:2025-08-03 Online:2025-12-26 Published:2025-08-28

摘要: 为满足毫米波雷达信号处理中对距离维和速度维进行高效、小点数二维快速傅里叶变换(2D-FFT)的需求,设计一种基于单路径延迟反馈的流水线架构2D-FFT加速引擎。该引擎在每级前引入数据选通模块,支持可配置的点数规模为M×N≤2 048。结果表明,该设计能够实现2D-FFT点数的灵活配置。所有2D-FFT运算结果的绝对误差<2.5,相对误差<0.5%,精度满足使用需求。与传统2D-FFT运算相比,该设计的计算效率显著提高。

关键词: 流水线, 单路径延迟反馈, 2D-FFT, 可配置点数

Abstract: To meet the demand for efficient, small-point two-dimensional fast Fourier transform (2D-FFT) in the distance and velocity dimensions of millimeter-wave radar signal processing, a pipelined architecture 2D-FFT acceleration engine based on single-path delay feedback is designed. This engine incorporates a data pick-and-pass module before each stage and supports configurable point sizes of M×N≤2 048. Results demonstrate that this design enables flexible configuration of 2D-FFT points. The absolute error of all 2D-FFT operation results is less than 2.5, and the relative error is less than 0.5%, which meets the accuracy requirements. Compared with the traditional 2D-FFT operation, the design achieves significantly improved computational efficiency.

Key words: pipeline, single-path delay feedback, 2D-FFT, configurable point

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