关键词: 并串转换, 收发器, 高速串行通信

Abstract: This article describes a high-speed, low-power 10:1 parallel-to-serial conversion chip based on the GSMC 130 nm CMOS . In the core parallel-serial conversion part, the chip uses a combination of a multi-phase structure and a tree structure to realize conversion of 10 channels of 500 Mbit/s parallel data to 1 channel of 5 Gbit/s serial data under the condition of inputting a half rate clock. After the complete chip is completed, the simulation results show that the chip can correctly complete the 10:1 parallel-to-serial conversion logic function at a working voltage of (1.2±10%) V and a temperature of -55-100 ℃ under full process angle, and the output is a clear 5 Gbit/s eye diagram. Under typical conditions, the overall power consumption of the chip is 25.2 mW, and the output voltage swing can reach 260 mV.

Key words: parallel-to-serial conversion, transceiver, high speed serial communication