关键词: 超深亚微米, 版图验证, 时序验证, 形式验证

Abstract: The layout design technology in SDSM digital ICs has evolved from simple physical verification to complicated layout verification. Layout verification consists of timing verification, formal verification and physical verification. The timing verification performs IR Drop analysis and timing analysis and ensures clock convergence. The formality verification performs equivalence checking of two net-lists. The physical verification performs DFM, reliability and design rule check and ensures that the layout complies with DFM rule and electric circuit rule. The verification technologies jointly guide and control the physical realization of digital ICs. Flexibly selection and collocation of layout verification technologies improve layout verification efficiency.

Key words: SDSM(super deep sub-mircon), layout verification, timing analysis, formality verification