关键词: 现场可编程门阵列;时钟架构;时钟管理

Abstract: In the FPGA design,the design and processing of the clock signal is an important part of the stability of the system.With the increasing size and integration level of FPGA devices,multi-clock domain management,clock delay, clock signal integrity and phase offset have become the key factors affecting FPGA design.The article presents a detailed analysis of the clock architecture and resource characteristics of the Virtex4 series chip of Xilinx Company.By referring the typical application of FPGA clock design,some tips and suggestions on clock design and usages are given.

Key words: FPGA, clock architecture, clock management