纳米级数字集成电路老化效应分析与老化监测技术综述*

doi:10.16257/j.cnki.1681-1070.2020.1005

摘要/Abstract

摘要： ?数字集成电路随着工艺制程的提高，可靠性问题逐步凸显，而老化则是可靠性问题的一个重要方面。同时由于数字集成电路被广泛地应用于工业、汽车、航天等领域，对可靠性提出更高的要求，因此针对数字集成电路老化监测的技术成为了研究热点。对数字集成电路的老化效应进行了总结，并分析得出先进工艺下需要重点监测的老化效应，对数字集成电路现有老化监测手段进行总结分析，同时对老化监测技术的进一步发展提出了展望。

关键词: ?数字集成电路, 可靠性, 老化监测

Abstract: ?With the improvement of the process of digital integrated circuits, reliability problems gradually become prominent, and aging is an important aspect of reliability problems. At the same time, because digital integrated circuits are widely used in industrial, automotive, aerospace and other fields, reliability is higher required, so the technology for aging monitoring of digital integrated circuits has become a research hotspot. The review summarizes and analyzes the aging effects of digital integrated circuits and obtains the aging effects that require key monitoring under advanced technology, and summarizes and analyzes the existing aging monitoring methods of digital integrated circuits and provides further development of aging monitoring technology some opinions.

Key words: digital integratedcircuits, reliability, aging monitor

中图分类号:

TN406

赵天津;黄乐天;谢暄;魏敬和. 纳米级数字集成电路老化效应分析与老化监测技术综述^*[J]. 电子与封装, 2020, 20(10): 100101 .

ZHAO Tianjin, HUANG Letian, XIE Xuan,WEI Jinghe. NanometerDigital Integrated Circuit Aging Effect Analysis and Aging MonitoringTechnology Review[J]. Electronics & Packaging, 2020, 20(10): 100101 .

参考文献

[1] KONG J T. Soc in nanoera: challenges and endless possibility[C]//Design, Automation and Test in Europe. IEEE, 2005.
[2] ?? BOWHILL B, STACKHOUSE B, NASSIF N, et al. The Xeon? processor E5-2600 v3: A 22 nm 18-core product family[J]. IEEE Journal of Solid-State Circuits, 2015, 51(1): 92-104.
[3] ?? MAIR H T, GAMMIE G, WANG A, et al. 4.3 A 20 nm 2.5 GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance[C]//2016 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2016: 76-77.
[4] ?? TAKAHASHI C, SHIBAHARA S, FUKUOKA K, et al. 4.5 A 16 nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10?7 random hardware failures per hour reliability[C]//2016 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2016: 80-81.
[5]???? HESS C, INANI A, JOAG A, et al. Stackable short flow characterization vehicle test chip to reduce test chip designs, mask cost and engineering wafers[C]//2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC). IEEE, 2010:328-333.
[6]???? MEIJER M, DE GYVEZ J P. Body-bias-driven design strategy for area-and performance-efficient CMOS circuits[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010, 20(1): 42-51.
[7] ?? BRAVAIX A, GUERIN C, HUARD V, et al. Hot-carrier acceleration factors for low power management in DC-AC stressed 40 nm NMOS node at high temperature[C]//2009 IEEE International Reliability Physics Symposium. IEEE, 2009: 531-548.
[8]???? WANG W, YANG S, BHARDWAJ S, et al. The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009, 18(2): 173-183.
[9]???? KEANE J, KIM C H. An odomoeter for CPUs[J]. IEEE Spectrum, 2011, 48(5): 28-33.
[10]?? BAUMANN R. Soft errors in advanced computer systems[J]. IEEE Design & Test of Computers, 2005, 22(3): 258-266.
[11] SENGUPTA D, SAPATNEKAR S S. Estimating circuit aging due to BTI and HCI using ring-oscillator-based sensors[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 36(10): 1688-1701.
[12] AMOURI A, BRUGUIER F, KIAMEHR S, et al. Aging effects in fpgas: an experimental analysis[C]//2014 24th international conference on Field Programmable Logic and Applications (FPL). IEEE, 2014: 1-4.
[13] NIGAM T. Impact of transistor level degradation on product reliability[C]//2009 IEEE Custom Integrated Circuits Conference. IEEE, 2009: 431-438.
[14] WANG W, REDDY V, KRISHNAN A T, et al. Compact modeling and simulation of circuit reliability for 65-nm CMOS technology[J]. IEEE Transactions on Device and Materials Reliability, 2007, 7(4): 509-517.
[15] SATO Y, KAJIHARA S, MIURA Y, et al. A circuit failure prediction mechanism (DART) for high field reliability[C]//2009 IEEE 8th International Conference on ASIC. IEEE, 2009: 581-584.
[16] WITTMANN R, PUCHNER H, HINH L, et al. Impact of NBTI-driven parameter degradation on lifetime of a 90nm p-MOSFET[C]//2005 IEEE International Integrated Reliability Workshop. IEEE, 2005: 4 .
[17] PARK M C, YANG G Y, YANG J S, et al. New perspective on lifetime prediction approach for BTI and HCI stressed device and its impact on circuit lifetime[C]//2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). IEEE, 2014: 337-340.
[18] STOTT E A, WONG J S J, SEDCOLE P, et al. Degradation in FPGAs: measurement and modelling[C]//Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays.2010: 229-238.
[19] ERNST D, KIM N S, DAS S, et al. Razor: A low-power pipeline based on circuit-level timing speculation[C]//Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36. IEEE, 2003: 7-18.
[20] DAS S, TOKUNAGA C, PANT S, et al. RazorII:In situ error detection and correction for PVT and SER tolerance[J]. IEEE Journal of Solid-State Circuits, 2008, 44(1): 32-48.
[21]?? 曹靓,田海燕,王栋.一种抗单粒子瞬态辐射效应的自刷新三模冗余触发器[J].电子与封装,2018,18(9):36-38，41.
[22] FOJTIK M, FICK D, KIM Y, et al. Bubble razor:An architecture-independent approach to timing-error detection and correction[C]//2012 IEEE International Solid-State Circuits Conference. IEEE,2012: 488-490.
[23] KWON I, KIM S, FICK D, et al. Razor-lite:A light-weight register for error detection by observing virtual supply rails[J]. IEEE Journal of Solid-State Circuits, 2014, 49(9): 2054-2066.
[24] SHAH N, SAMANTA R, ZHANG M, et al. Built-in proactive tuning system for circuit aging resilience[C]//2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems. IEEE,2008: 96-104.
[25] VALDES-PENA M D, FREIJEDO J F, RODRIGUEZ M J M, et al. Design and validation of configurable online aging sensors in nanometer-scale FPGAs[J]. IEEE transactions on nanotechnology, 2013, 12(4): 508-517.
[26]?? 胡鹏,魏江杰,周昱,等.基于环形振荡器的物理不可克隆函数的设计与验证[J].电子与封装,2019,19(7):33-36.
[27] NOURANI M, RADHAKRISHNAN A. Testing on-die process variation in nanometer VLSI[J]. IEEE Design & Test of Computers,2006, 23(6): 438-451.
[28] WANG X, TEHRANIPOOR M, DATTA R. Path-RO: A novel on-chip critical path delay measurement under process variations[C]//2008 IEEE/ACM International Conference on Computer-Aided Design. IEEE, 2008: 640-646.
[29] WANG X, TEHRANIPOOR M, DATTA R. A novel architecture for on-chip path delay measurement[C]//2009 International Test Conference. IEEE, 2009: 1-10.
[30] WANG X, TEHRANIPOOR M, GEORGE S, et al.Design and analysis of a delay sensor applicable to process/environmental variations and aging measurements[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011, 20(8): 1405-1418.
[31] LI J, SEOK M. Robust and in-situ self-testing technique for monitoring device aging effects in pipeline circuits[C]//Proceedings of the 51st Annual Design Automation Conference. 2014:1-6.
[32] KEANE J, WANG X, PERSAUD D, et al. An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB[J]. IEEE Journal of Solid-State Circuits, 2010, 45(4): 817-829.
[33]?? 张海明,汪鹏君,张跃军.基于查找表的电路老化检测传感器设计[J].宁波大学学报(理工版),2019,32(4):25-31.
[34] TSCHANZ J, BOWMAN K, WALSTRA S, et al. Tunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance[C]//2009 Symposium on VLSI Circuits. IEEE, 2009: 112-113.
[35]?? 魏敬和,林军. 深度学习算法、硬件技术及其在未来军事上的应用[J].电子与封装,2019,19(12):1-6, 22.
[36] VIJAYAN A, KONERU A, KIAMEHR S, et al.Fine-grained aging-induced delay prediction based on the monitoring of run-time stress[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 37(5): 1064-1075.
[37] VIJAYAN A, KIAMEHR S, EBRAHIMI M, et al. Online soft-error vulnerability estimation for memory arrays and logic cores[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 37(2): 499-511.
[38] FIROUZI F, YE F, CHAKRABARTY K, et al.Representative critical-path selection for aging-induced delay monitoring[C]//2013 IEEE International Test Conference (ITC). IEEE, 2013: 1-10.
[39] WANG H, HUANG D, LIU R, et al. STREAM:stress and thermal aware reliability management for 3-D ICs[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 38(11): 2058-2071.
[40] HUANG K, ZHANG X, KARIMI N. Real-time prediction for IC aging based on machine learning[J]. IEEE Transactions on Instrumentation and Measurement, 2019, 68(12): 4756-4764.
[41] VIJAYAN A , KIAMEHR S , OBORIL F , et al.Workload-aware static aging monitoring and mitigation of timing-critical flip-flops[J]. IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems, 2018, 37(10):2098-2110.
[42]?? 阮莹,梁利娟. 数字集成电路老化故障高精度预测方法仿真[J].计算机仿真,2020,37(2):434-437.

中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

纳米级数字集成电路老化效应分析与老化监测技术综述^*

NanometerDigital Integrated Circuit Aging Effect Analysis and Aging MonitoringTechnology Review

RichHTML

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 15

编辑推荐

Metrics

本文评价

[1]	王亚男;张洪伟;王文炎;常明超. 一种蝶形封装多路光收发模块可靠性评价与应用研究[J]. 电子与封装, 2024, 24(8): 80204-.
[2]	史兴强,刘梦影,王芬芬,陆皆晟,陈红. 一种基于汉明码纠错的高可靠存储系统设计[J]. 电子与封装, 2024, 24(7): 70301-.
[3]	吴鲁超,陆宇青,王珺. 硅通孔3D互连热-力可靠性的研究与展望^*[J]. 电子与封装, 2024, 24(6): 60103-.
[4]	武荣荣,梅亮,任翔,曹阳,庞明奇,刘净月. 首次选用的典型裸芯片应用可靠性评价方法[J]. 电子与封装, 2024, 24(5): 50204-.
[5]	徐达,戎子龙,杨彦锋,魏少伟,马紫成. 基于ENEPIG镀层的无压纳米银膏烧结失效分析[J]. 电子与封装, 2024, 24(4): 40204-.
[6]	曹玉翠,刘钊,汪小勇,李泽宇. 车规电子零缺陷质量管理在航天领域的启发与推广[J]. 电子与封装, 2024, 24(4): 40502-.
[7]	张永华,曲芳,何浒澄. 国产电容器的质量评价方法[J]. 电子与封装, 2024, 24(3): 30202-.
[8]	梁梦楠,陈志强,张国杰,姚昕,李轶楠,张爱兵. 有机封装基板界面处理工艺对结合强度与可靠性的影响[J]. 电子与封装, 2024, 24(2): 20105-.
[9]	田文超;谢昊伦;陈源明;赵静榕;张国光. 人工智能芯片先进封装技术[J]. 电子与封装, 2024, 24(1): 10204-.
[10]	张俊,程佳,林子群,徐延伸. 光伏二极管应用可靠性建模与评价研究[J]. 电子与封装, 2023, 23(9): 90405-.
[11]	王刘珏, 顾林, 郑利华, 李居强. 纳米银焊膏贴装片式电阻的可靠性研究^*[J]. 电子与封装, 2023, 23(8): 80204-.
[12]	陈婷, 周伟洁, 王涛. 微波等离子处理对导电胶可靠性的影响[J]. 电子与封装, 2023, 23(8): 80206-.
[13]	沈丹丹. 先进封装中凸点技术的研究进展[J]. 电子与封装, 2023, 23(6): 60208-.
[14]	李嘉威;吴楚彬;王超;孙杰杰;杨霄垒;赵桂林. 应用于STT-MRAM存储器的高可靠灵敏放大器设计[J]. 电子与封装, 2023, 23(4): 40306-.
[15]	申九林, 马书英, 郑凤霞, 王姣, 魏浩. 基于硅基扇出（eSiFO^®）技术的先进指纹传感器晶圆级封装工艺开发[J]. 电子与封装, 2023, 23(3): 30111-.