关键词: 时序参数, FPGA, 静态时序分析

Abstract: Static timing analysis is a vital functionality in FPGA development and application, which verifies the timing constraints on user’s design. The parameters that the STA software needs directly influence the validity of result. This paper introduces a method that combines simulation and actual measurement to extract timing accurate parameters. The experiment results show that the software timing parameters based on the independent FPGA chip can accurately reflect the timing of chip through the STA analysis and meet the domestic software timing parameters replacement requirements.

Key words: timingmodelparameters, FPGA, statictiminganalysis