关键词: I2C总线, SMBus总线, SOC, Verilog HDL

Abstract: An I2C bus controller compatible with SMBus protocol 2.0 is proposed to meet the Intelligence Property reuse technology of SOC with high performance and low cost. The design not only ensures functions and timing of I2C and SMBus, but greatly saves hardware resources. It can be widely used in the peripheral communication environment of both of I2C and SMBus. In addition, the design is based on APB interface and the implementation of Verilog HDL, which can be easily integrated into SOC system. Finally, the compatibility of I2C bus controller is verified, and its bus function perfection, bus timing specification and bus communication stability are proved.

Key words: I2C bus, SMBus, SOC, Verilog HDL