关键词: A/D转换器, 高速, 逐次逼近ADC, 电容分裂, MSB电容减小

Abstract: In this paper, an 8-Bit 51 MS/s SAR-ADC in 180 nm CMOS Process is designed. With the improved structure of DAC, not only does the impact of the MSB capacitance on the speed of SAR ADC decreases, but also the efficiency of the high-speed clocked-comparator raised. The simulation results show that the SNDR of the ADC is 44.3 dB, the SFDR is 51.6 dB, and the ENOB is 7.07 dB at 25 MHz input signal frequency and 51 MHz sample clock frequency. The total power dissipation of this converter is 0.61 mW, and the FOM is 89 fJ/conv with a 1.8 V supply. Based on fixed unit capacitance, the design in this paper doubles the speed compared to the original structure with only one more register and 0.05 mW more power consumption.

Key words: Analog-to-digital converter, high speed, SAR ADC, capacitance split, the MSB capacitance decreasing