中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装

• 电路与系统 •    下一篇

基于RISC-V的抗单粒子加固研究

徐文龙,李凯旋,许峥,姚进,周昕杰   

  1. 中国电子科技集团公司第五十八研究所,江苏 无锡  214035
  • 收稿日期:2025-06-30 修回日期:2025-08-28 出版日期:2025-09-08 发布日期:2025-09-08
  • 通讯作者: 徐文龙

Research on Single Event Upset Hardening Based on RISC-V

XU Wenlong, LI Kaixuan, XU Zheng, YAO Jin, ZHOU Xinjie   

  1. China Electronics Technology Group Corporation No.58 Research Institute, Wuxi 214035, China
  • Received:2025-06-30 Revised:2025-08-28 Online:2025-09-08 Published:2025-09-08

摘要: 在现代电子器件和集成电路设计中,单粒子效应已成为一个不可忽视的问题。基于RISC-V精简指令集,利用三模冗余和检错纠错技术,进行了多层次的抗辐射加固。对加固后的电路流片,并开展辐射试验。试验结果显示该电路在地球静止轨道(GEO)单粒子翻转率小于10-4 error/(device·day),单粒子闩锁阈值大于75 MeV·cm2/mg,验证了抗单粒子翻转和单粒子闩锁加固措施的有效性。

关键词: 单粒子翻转, 单粒子闩锁, 抗辐射加固

Abstract: In modern electronic devices and integrated circuit design, single event effects have become an issue that cannot be ignored. RISC-V IP has undergone multi-level radiation hardening in this paper, including triple modular redundancy and error detection and correction. In addition, the integrated circuit is fabricated and then subjected to radiation experiments. The experimental results indicate that the single event upset rate in GEO orbit is less than 10-4 error/(device·day), and the single event latch-up threshold is greater than 75 MeV·cm2/mg, confirming the effectiveness of single event upset  and single event latch-up hardened design.

Key words: single event upset, single event latch-up, radiation hardened