基于硅转接板的2.5D封装中电源地平面研究和优化

doi:10.16257/j.cnki.1681-1070.2025.0151

电子与封装 ›› 2025, Vol. 25 ›› Issue (11): 110201 . doi: 10.16257/j.cnki.1681-1070.2025.0151

基于硅转接板的2.5D封装中电源地平面研究和优化

陈龙¹，宋昌明¹，周晟娟²，章莱³，王谦^1,4，蔡坚^1,4

1. 清华大学集成电路学院，北京 100084；2. 上海清华国际创新中心，上海 200333；3. 北京芯力技术创新中心有限公司，北京 100176；4. 北京信息科学与技术国家研究中心，北京 100084

收稿日期:2025-04-14 出版日期:2025-11-28 发布日期:2025-06-25
作者简介:陈龙（2000—），男，福建福州人，硕士研究生，主要研究方向为电子封装信号完整性、电源完整性。

Research and Optimization of Power and Ground Planes in 2.5D Packaging Based on Silicon Interposer

CHEN Long¹, SONG Changming¹, ZHOU Shengjuan², ZHANG Lai³, WANG Qian^1,4, CAI Jian^1,4

1. School of Integrated Circuits, Tsinghua University, Beijing 100084,China; 2. International Innovation Center of Tsinghua University, Shanghai 200333, China; 3. Beijing Xinli Technology Innovation Center Co., Ltd., Beijing 100176,China; 4. Beijing National Research Center for InformationScience and Technology, Beijing100084, China

Received:2025-04-14 Online:2025-11-28 Published:2025-06-25

摘要/Abstract

摘要： 针对基于硅转接板的2.5D封装中电源分配网络（PDN）阻抗大、系统电压噪声大的电源完整性问题，建立2.5D封装模型，研究和优化封装系统的电源完整性。采用三维电磁场与电路协同仿真的方法，对硅转接板上的电源地平面进行阻抗优化，并通过合理选择与布局深槽电容（DTC）对系统进行阻抗优化和电压噪声改善。结果显示，提高电源地平面的布线密度能够有效降低PDN的阻抗。电源地平面线宽/线距存在优化下限，当线宽/线距小于片间互连信号线线宽的2倍时会对片间互连信号线产生阻抗不连续的不良影响。在所建立的模型中，根据PDN阻抗的高频谐振峰选择DTC，使得PDN阻抗降低约83%，电压噪声减小约42%。同时，DTC的集成会在中高频段引入新的谐振峰，对PDN产生阻抗增大的不利影响。

关键词: 2.5D封装, 硅转接板, 电源完整性, 电源地平面, 深槽电容

Abstract: Aiming at the power integrity issues of large impedance of the power delivery network (PDN) and large system voltage noise in the 2.5D packaging based on the silicon interposer, a 2.5D packaging model is established for studying and optimizing the power integrity of the packaging system. A method of collaborative simulation of three-dimensional electromagnetic fields and circuits is adopted to optimize the impedance of the power and ground planes on the silicon interposer. System impedance is optimized and voltage noise is reduced by reasonably selecting and arranging deep trench capacitors (DTCs). The results show that increasing the wiring density of the power and ground planes can effectively reduce the impedance of the PDN. There is an optimization lower limit for the line width/line spacing of the power and ground planes. When the line width/line spacing is less than twice the line width of the signal lines, it will have an adverse effect of impedance discontinuity on the die-to-die interconnect signal lines. In the established model, the DTCs are selected according to the high-frequency resonance peaks of the PDN impedance, reducing the PDN impedance by approximately 83% and decreasing the voltage noise by about 42%. At the same time, the integration of DTCs will introduce new resonance peaks in the medium and high frequency bands, which has an adverse effect of large impedance on the PDN.

Key words: 2.5D packaging, silicon interposer, power integrity, power and ground planes, deep trench capacitor

中图分类号:

陈龙，宋昌明，周晟娟，章莱，王谦，蔡坚. 基于硅转接板的2.5D封装中电源地平面研究和优化[J]. 电子与封装, 2025, 25(11): 110201 .

CHEN Long, SONG Changming, ZHOU Shengjuan, ZHANG Lai, WANG Qian, CAI Jian. Research and Optimization of Power and Ground Planes in 2.5D Packaging Based on Silicon Interposer[J]. Electronics & Packaging, 2025, 25(11): 110201 .

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中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

基于硅转接板的2.5D封装中电源地平面研究和优化

Research and Optimization of Power and Ground Planes in 2.5D Packaging Based on Silicon Interposer

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