关键词: 2.5D封装, 再布线层, 微凸点, 硅通孔, 铜铜直接键合

Abstract: As Moore’s law approaches its physical limits in transistor scaling, advanced packaging technologies have emerged as a pivotal pathway to overcome performance bottlenecks through system miniaturization and heterogeneous integration. As a critical branch of advanced packaging, 2.5D packaging enables high-density interconnects and multi-chip heterogeneous integration via silicon/glass interposers, offering advantages in high bandwidth, low latency, and compact form factors, which are widely adopted in artificial intelligence (AI), high-performance computing (HPC), and mobile electronics. This paper systematically elaborates the core architectures of 2.5D packaging (e.g., CoWoS, EMIB, and I-Cube) and their technical characteristics, with a focused analysis of the latest advancements in key technologies. These include modular design of chiplets, process optimization of through-silicon vias (TSVs), reliability enhancement of microbumps, interface engineering of Cu-Cu direct bonding, and multi-physics co-design of redistribution layers (RDLs). Future researches should focus on low-cost glass substrates, atomic layer deposition (ALD) enabled interface engineering, and multi-physics co-design methodologies to overcome yield and thermal management bottlenecks, thereby accelerating the adoption of 2.5D packaging in high-performance computing scenarios within the post-Moore era.

Key words: 2.5D packaging, redistribution layer, micro bump, through silicon via, Cu-Cu direct bonding