关键词: FlashFPGA, 锁相环, 时钟网络

Abstract: A Flash FPGA clock network architecture based on phase-locked loop (PLL)  is designed. The number of global clocks is expanded to three, and two additional core-output clocks are added in this architecture. One PLL-equipped clock conditioning circuit and five non-PLL clock conditioning circuits are implemented around the chip periphery to achieve frequency division, frequency multiplication, phase shift, and delay functions. Simulation results demonstrate that this architecture can meet the timing configuration requirements of the entire chip. Actual tape-out tests indicate that the maximum operating frequency of the architecture reaches 350 MHz, a significant improvement over the original clock conditioning circuit (180 MHz) and comparable to that of similar-scale international products.

Key words: Flash FPGA, phase-locked loop, clock network