关键词: Flash FPGA, 锁相环, 时钟网络

Abstract: A clock network architecture based on phase-locked-loop was designed specifically for Flash FPGA. The clock-control circuit with phase-locked loop (PLL) increased the global clock to 3, and added 2 additional core output clocks. Additionally, 5 clock-control circuits (CCC) without PLL were designed around the chip to achieve frequency division, multiplication, phase shift, and delay operations. Through simulation, the clock network can meet the timing configuration requirements of entire chip; In actual chip testing, the maximum operating frequency of the clock-control circuit network architecture can reach 350 MHz, and the designed clock adjustment circuit can reach a maximum operating frequency of 180 MHz, which is significantly improved and comparable to similar and scaled products abroad (with a maximum operating frequency of 350 MHz), reaching the level of foreign counterparts.

Key words: Flash FPGA, Phase-Locked Loop, Clock Network