关键词: SARADC, 高速, VCM开关切换策略, 动态比较器

Abstract: A high-speed successive approximation register (SAR) analog-to-digital converter (ADC) based on common mode voltage (VCM) switching strategy is proposed. An improved dual-tailed current source dynamic comparator is employed, featuring a dual-current-source cross-latch structure that accelerates comparison speed while eliminating static power consumption, thereby enhancing the overall speed of the SAR ADC. Simultaneously, the VCM switching strategy resolves excessive power consumption during capacitor array switching and common-mode drift at the comparator input. Capacitor splitting technology overcomes the difficulty of designing VCM levels independently and reduces the complexity of the switching timing logic design. Based on the SMIC 130 nm process, simulations are conducted for a 1 024-point fast Fourier transform (FFT) at a 1.2 V supply voltage and 50 MSample/s sampling rate. Results show that at the low input frequency (244.14 kHz), the ADC achieves an effective number of bits (ENOB) of 9.73 bit, a signal-to-noise distortion ratio (SNDR) of 60.34 dB, a spurious-free dynamic range (SFDR) of 73.72 dBc, and a total power consumption of 0.95 mW.

Key words: SAR ADC, high-speed, VCM switching strategy, dynamic comparator