关键词: JESD204B, 多通道, 高速, SiP, 性能

Abstract: Research on high-speed system level package (SiP) processing chips has important practical application value for the development of modern high-speed data processing field. Aiming at the problems of low channel number, low integration, large occupation area, and easy interference in current high-speed processing systems, this paper proposes a high-speed SiP processing chip that takes field programmable gate array (FPGA) as the core, integrates eight channels of acquisition and eight channels of output, and supports the standardized serial interface transmission of "Joint Commission on Electronic Devices Engineering Standard 204B" (JESD204B). The internal analog-to-digital converter (ADC) and digital to analog converter (DAC) are high-speed acquisition chips, which support JESD204B interface protocol, and the serial device (SERDES) speed can reach up to 10 Gbit/s, enabling fast data transmission and efficient signal processing. This paper deeply analyzes the architecture and performance parameters of the SiP processing chip. The actual measured overall area of the chip is only 20.25 cm², the maximum input sampling and output sampling can reach 1 GFrame/s and 2.4 GFrame/s respectively, and the channel isolation is about 75 dB. At the same time, a clock chip plug-in architecture strategy is proposed, which effectively improves the high temperature resistance of the chip, and further expands the application scenarios and application environments of this kind of high-speed SiP chips.

Key words: JESD204B, multi-channel, high-speed, SiP, performance