中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2022, Vol. 22 ›› Issue (1): 010302 . doi: 10.16257/j.cnki.1681-1070.2022.0108

• 电路与系统 • 上一篇    下一篇

基于SiP技术多片DDR3高速动态存储器设计

张小蝶1;邱颖霞1,2;许聪1,2;邢正伟1   

  1. 1.? 安徽芯纪元科技有限公司,合肥 230093;2.中国电子科技集团公司第三十八研究所,合肥 230031
  • 收稿日期:2021-06-24 出版日期:2022-01-25 发布日期:2021-08-25
  • 作者简介:张小蝶(1993—),女,安徽蚌埠人,硕士,工程师,主要从事系统级高速电路设计以及电源/信号完整性仿真验证工作。

Design ofMulti-Chip DDR3 High-Speed Dynamic Memory Based on SiP Technology

ZHANG Xiaodie1, QIU Yingxia1,2, XU Cong1,2, XING Zhengwei1   

  1. 1. Anhui SiliepochTechnology Co., Ltd, Hefei 230031, China; 2. The 38thResearch Institute of CETC, Ltd,Hefei 230031, China
  • Received:2021-06-24 Online:2022-01-25 Published:2021-08-25

摘要: 基于系统级封装技术(System in Package,SiP),结合自研自主可控DSP处理器“魂芯”II-A和多片DDR3颗粒,详细介绍了一款高速动态存储控制一体化SiP设备的设计方案和仿真验证分析结果,重点介绍了此款SiP的电路拓扑设计、版图设计,并从拓扑结构波形仿真、DDR3时序裕量计算和与板级实现方案对比三方面对其PCB后仿进行了分析和验证,仿真结果符合规范要求,证明了所采用的Fly-By拓扑适用于CPU与多片DDR3颗粒所组成的一体化SiP设备,且SiP设备性能优于板级实现方案。

关键词: DDR3, 高速电路, SiP, 信号完整性, Sigrity仿真

Abstract: Based on the system in package (SiP for short) technology. Combined with a self-developed independent controllable DSP processor (“HX” II-A) and multi-chip DDR3 particles. Moreover, this paper introduces in detail the design scheme and simulation verification analysis of a device result, a kind of high-speed dynamic memory control integrated SiP. The paper focuses on the circuit topology design and the layout design of this SiP, then it verifies its PCB post-simulation from three aspects, including topology simulation waveform, DDR3 timing margin calculation, and comparison with board-level implementation schemes. Finaly, the simulation results are compounded and standardized, and the requirements prove that the adopted Fly-By topology is suitable for integrated SiP equipment which is composed of CPU and multiple DDR3 particles. In addition, the performance of SiP equipment is better than the board-level implementation scheme.

Key words: DDR3, high-speedcircuit, SiP, signalintegrity, Sigritysimulation

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