关键词: 现场可编程门阵列, 布线, 引脚重构, 初始解, 拥塞

Abstract: The routing method based on initial solution optimization is proposed for self-design field programmable gate array (FPGA). According to the logic chip routing structure, the logic cell pins of the netlist are reconstructed by simple pattern matching to generate initial solutions with low routing congestion. The routing strategy combining the nodes and sinks is used in the routing progress to accelerate the convergence of the solution. Experimental results show that the proposed method reduces the number of congestion by 16.6% in the global routing stage, decreases the cumulative number of congestion by 9.8% in the detail routing stage, reduces the running time by 7.8% and improves the critical path margin by 17.2%.

Key words: FPGA, routing, pin reconfigure, initialsolution, congestion