关键词: 流水线模数转换器, 时钟产生, 时钟接收

Abstract: A Low jitter multi-phase clock generator for high speed pipelined ADC is presented.In order to reject the clock jitter,the high sensitivity differential clock input structure and clock receiver is used.A 12-bit 250 MSPS pipelined ADC based on the proposed sub-stage circuit is presented.The ADC is manufactured in 0.18 μm 1P5M 1.8 V CMOS process,with a die area of 2.5 mm2.The test result shows that the ADC achieves an SNR of 69.92 dB,an SFDR of.81.17 dB,an INL of-0.4 to+0.65 LSB,a DNL of-0.2 to+0.15 LSB and a power consumption of 320 mW for 20 MHz input at full sampling speed.

Key words: pipelined analog-to-digital converter, clock generator, clock receiver