关键词: LDMOS, 双回滞, 鲁棒性

Abstract: LDMOS is widely used in high voltage ICs by reason of its high output power, high gain, high linearity and excellent heat stability. The ESD robustness of LDMOS devices may be weakened by the double snapback occurred in the high voltage ESD protection process. The LDMOS device analyzed in the article is fabricated in 0.25 μm Bipolar-CMOS-DMOS process. The failure and weak robustness are mainly caused by the peak electric field transfer. To solve the problem, the layout of LDMOS is modified using the P+ instead of the N+. The TLP test results indicate that the leakage current remains the level of 10-8 A and the second failure current is more than 9A. The robustness of the optimized LDMOS can be effectively strengthened due to the suppressed double snapback, providing a suitable ESD protection solution for high-voltage power integrated circuits.

Key words: LDMOS, double snapback, robustness