700 V超低比导通电阻的LDMOS器件

doi:10.16257/j.cnki.1681-1070.2020.0804

电子与封装 ›› 2020, Vol. 20 ›› Issue (8): 080401 . doi: 10.16257/j.cnki.1681-1070.2020.0804

700 V超低比导通电阻的LDMOS器件

李怡，乔明

电子科技大学电子薄膜与集成器件国家重点实验室，成都 610054

接受日期:2020-02-13 出版日期:2020-08-25 发布日期:2020-04-10
作者简介:李　怡（1995—），女，山西晋中人，电子科技大学硕士研究生，2017年电子科技大学微电子科学与技术专业本科毕业，目前从事高压功率集成技术、功率器件等研究工作。

700 V Ultra-Low Specific on-Resistance LDMOS

LI Yi, QIAO Ming

State Key Laboratory of Electronic Thin Films and Integrated Device, UESTC, Chengdu 610054, China

Accepted:2020-02-13 Online:2020-08-25 Published:2020-04-10

摘要/Abstract

摘要： LDMOS器件广泛应用于高压集成电路芯片中，由于常作为功率开关来使用，其主要的性能指标为击穿电压（V_B）与比导通电阻（R_ON,sp）。然而，V_B与R_ON,sp均强烈受制于漂移区长度及掺杂浓度，因此存在固有的矛盾关系。Triple RESURF技术被广泛使用于优化器件V_B与R_ON,sp之间的矛盾关系。基于传统Triple RESURF技术，提出了一种新型Triple RESURF LDMOS结构，即在P-buried层的上方和下方引入了高浓度的 N 型掺杂层。相较于传统结构，该结构器件既可以避免表面杂质浓度较高带来的器件提前击穿，又可以降低同等电压下的比导通电阻。测试结果表明该结构可以达到V_B=795 V, R_ON,sp=78.3 mΩ?cm²，相比于传统结构的R_ON,sp降低了26.8%。

关键词: LDMOS, Triple RESURF, 比导通电阻, 击穿电压

Abstract: LDMOS devices are widely used in high voltage integrated circuit chips. Because LDMOS are often used as power switches, the main performance indicators are breakdown voltage (V_B) and specific on-resistance (R_ON,sp). However, V_B and R_ON,sp are strongly subject to the length of drift zone and doping concentration, so there is an inherent contradictory relationship between V_B and R_ON,sp. Triple RESURF technology is widely used to optimize the contradictory relationship between V_B and R_ON,sp. Based on the traditional Triple RESURF technology, a new Triple RESURF LDMOS structure is proposed, which introduces high concentration N-type layer above and below the P-buried layer. Compared with the traditional structure, this structure can not only avoid the premature avalanche breakdown of the device caused by high surface impurity concentration, but also reduce the specific on-resistance under the same voltage. Test results show that the structure can achieve V_B=795 V, R_ON,sp=78.3 mΩ?cm², and compared with the traditional structure, R_ON,sp was reduced by 26.8%.

Key words: LDMOS, Triple RESURF, specific on-resistance, breakdown voltage

中图分类号:

TN306

李怡，乔明. 700 V超低比导通电阻的LDMOS器件[J]. 电子与封装, 2020, 20(8): 080401 .

LI Yi, QIAO Ming. 700 V Ultra-Low Specific on-Resistance LDMOS[J]. Electronics & Packaging, 2020, 20(8): 080401 .

参考文献

[1] 李燕妃，吴建伟，顾祥,等. 30 V NLDMOS结构优化及SEB能力提高[J].电子与封装，2018,18（10）：36-39.
[2] 余洋，乔明. 一种SOI LDMOS器件辐射效应仿真研究[J].电子与封装，2018,18（7）：32-34.
[3] APPELS J A, VAES H M J. High voltage thin layer devices (RESURF devices) [C]. IEEE International Electron Devices Meeting, 1979:238-241.
[4] KITAMURA A, WATANABE Y, OGINO M, et al. A high density, low on-resistance 700 V class trench offset drain LDMOSFET (TOD-LDMOS) [C]. IEEE International Electron Devices Meeting, 2003.
[5] VAES H M J, APPELS J A. High voltage high current lateral devices (RESURF devices) [C]. IEEE International Electron Devices Meeting, 1980:87-90.
[6] SHEU G, HUANG C. A study of low cost 1200 V linear P-top LDMOS device [C]. IEEE International Conference of Electron Devices and Solid-State Circuits, 2017.
[7] DISNEY D R, PAUL A K, DARWISH M, et al. A new 800 V lateral MOSFET with dual conduction paths [C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2001:399-340.
[8] IQBAL M M, UDREA F, NAPOLI E. On the static performance of the RESURF LDMOSFETS for power ICS [C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2009:247-250.
[9] QIAO M, YU L, DAI G, et al. Design of a 700 V DB-nLDMOS based on substrate termination technology[J]. IEEE Transactions on Electron Device, 2015, 62(12):4121-4127.
[10] QIAO M, LI C, LIU Y, et al. Design of a novel triple reduced surface field LDMOS with partial linear variable doping n-type top layer[J]. Superlattices and Microstructures, 2016, 93:242-247. [11] LEE S H, JEON C K, MOON J W, et al. 700V Lateral DMOS with new source fingertip design[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2008:141-144. [12] SU R Y, YANG F J, TSAY J L, et al. State-of-the-art device in high voltage power ICs with lowest on-state resistance[C]. IEEE International Electron Devices Meeting, 2010. [13] KIM S, KIM J, PROSACK H. Novel lateral 700 V DMOS for integration: Ultra-low 85 mΩ?cm2 on-resistance, 750 V LFCC[C]. IEEE International Symposium on Power Semiconductor Devices and ICs, 2012:185-188. [14] YANG F J, GONG J, SU R Y, et al. A 700-V device in high-voltage power ICs with low on-state resistance and enhanced SOA[J]. IEEE Transactions on Electron Devices, 2013, 60(9):2947-2853. [15] MAO K, QIAO M, LI Z, et al. 700 V ultra-low on-resistance DB-nLDMOS with optimized thermal budget and neck region[J]. IEEE Electron Device Letter, 2014, 50(3):209-211. [16] SAI S K, SHEU G, SELVENDRAN S, et al. Linear P-top technology for 600-800 V ultra high voltage BCD integration process[C]. IEEE International Symposium on Next Generation Electronics, 2017:1-4.

中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

700 V超低比导通电阻的LDMOS器件

700 V Ultra-Low Specific on-Resistance LDMOS

RichHTML

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 15

编辑推荐

Metrics

本文评价

[1]	卓宁泽;赖信彰;于世珩. 多重场限环型终端结构的优化设计^*[J]. 电子与封装, 2023, 23(2): 20402-.
[2]	鞠久贵;成爱强. 基于负载牵引的S波段130 W硅LDMOS功率放大器研制[J]. 电子与封装, 2023, 23(1): 10301-.
[3]	周淼, 汤亮, 何逸涛, 陈辰, 周锌. 一种部分超结型薄层SOI LIGBT器件的研究^*[J]. 电子与封装, 2022, 22(9): 90403-.
[4]	马红跃，方健，雷一博，黎明，卜宁，张波. 一种总剂量辐照加固的双栅LDMOS器件[J]. 电子与封装, 2021, 21(8): 80401-.
[5]	潘福跃;张明新;曹利超;刘佰清;洪根深;张海良;刘国柱. ONO反熔丝器件可编程特性研究[J]. 电子与封装, 2021, 21(7): 70404-.
[6]	师锐鑫;周锌;乔明;王卓;李燕妃. SOI高压LDMOS单粒子烧毁效应机理及脉冲激光模拟研究^*[J]. 电子与封装, 2021, 21(11): 110404-.
[7]	敖国军，廖小平，杨兵. 磁耦数字隔离器陶瓷封装技术研究[J]. 电子与封装, 2020, 20(8): 80202-.
[8]	孟培培,乔明. 一种250 V高动态阻抗恒流器件优化设计[J]. 电子与封装, 2020, 20(6): 60401-.
[9]	马阔,乔明,周锌,王卓. 高压SOI pLDMOS器件电离辐射总剂量效应研究[J]. 电子与封装, 2020, 20(6): 60403-.
[10]	何林蓉,乔明. 基于双极载流子导电的新型恒流器件[J]. 电子与封装, 2020, 20(5): 50403-.
[11]	陈正才;黄龙;彭时秋. 5 V双向TVS器件击穿电压对称性分析与优化设计[J]. 电子与封装, 2020, 20(10): 100404-.
[12]	杨昆;乔明;何俊卿;王睿. 横向超结器件耐压与比导的优值仿真与实验验证[J]. 电子与封装, 2020, 20(10): 100401-.
[13]	张恩阳，黄勇，孟令锋，代高强. 基于共享Buffer的LIGBT和PLDMOS器件研究[J]. 电子与封装, 2018, 18(2): 46-48.
[14]	李燕妃，吴建伟，顾　祥，洪根深. 30 V NLDMOS结构优化及SEB能力提高[J]. 电子与封装, 2018, 18(10): 36-39.
[15]	王涛，黄龙，潘建华，赵秋森. LDMOS器件ESD防护特性分析与优化设计[J]. 电子与封装, 2017, 17(8): 41-43.