中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2017, Vol. 17 ›› Issue (9): 28 -31. doi: 10.16257/j.cnki.1681-1070.2017.0110

• 电路设计 • 上一篇    下一篇

一种减小数字时钟延时单元温漂的方法

涂波1,赵晓静1,谢长生2   

  1. 1. 中国电子科技集团公司第五十八研究所,江苏 无锡 214072; 2. 无锡中微亿芯有限公司,江苏 无锡 214072
  • 出版日期:2017-09-20 发布日期:2017-09-20
  • 作者简介:涂波(1985—),男,四川南充人,本科,工程师,研究方向为千万门级FPGA 设计与验证。

A Method of Reducing the Delay Temperature Drift for Digital Clock Delay-cells

TU Bo1, ZHAO Xiaojing1, XIE Changsheng2   

  1. 1.China Electronics Technology Group Corporation No.58 Research Institute, Wuxi 214072, China; 2. East Technologies, inc. Wuxi 214072, China
  • Online:2017-09-20 Published:2017-09-20

摘要: 介绍了一种减小数字时钟延时单元温漂的方法,利用一个具有正温度系数的带隙基准电压源Bandgap,产生参考电压VREF;电压缓冲器LDO接收参考电压VREF并作用于延迟链;延迟链由延迟单元TAP串联而成,用来产生时钟的相位延迟。通过调整Bandgap的正温度系数,使LDO的输出电压随温度升高而升高,升高的电压会使延迟单元TAP的延时减小,从而抵消延迟单元TAP由于温度升高而增大的延时。

关键词: 延时单元, 温漂, 带隙基准, LDO

Abstract: In the paper, a design reducing the delay temperature drift of digital clock delay-cellis described, which includes a Bandgap reference voltage(VREF) generator having a positive temperature coefficient, a LDO which receives the VREF and power the delay line. The delay line contains a series of delay-cells and used for shift the clock phase. By a positive temperature coefficient of Bandgap designed, the delay-cell power voltage will change same direction with temperature, which compensates the delay variation of delay-cell caused by the changed temperature.

Key words: delay-cell, temperature drift, bandgap, LDO

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