关键词: 时间数字转换器, 高精度, FPGA, 进位链, 抽头延迟线

Abstract: High-precision time interval measurement is a key technology in various scientific and engineering fields such as laser ranging, radar, and oscilloscopes. In order to improve the accuracy of the measurements, an FPGA tap delay chain is used to implement a high-precision time to digital converter (TDC). Measurements of complete and incomplete clock cycles are achieved through pulse counting and tap delay line methods. A method is proposed to measure the delay chain accuracy using phase locked loop (PLL) dynamic phase modulation function, with a PLL phase modulation accuracy of 15.625 ps. The measurement error introduced by PLL phase modulation accuracy is reduced by averaging over multiple delay chain cascades, with a minimum measurement error of 0.3125 ps. The design of TDC is achieved using the Pango Logos2 series FPGA chip, the simulation verification and board-level test results prove that the measurement of incomplete clock cycles is achieved using a 50-level delay chain, with a measurement accuracy of 71 ps, and the measurement range of TDC time interval is less than 4.295 0 ms.

Key words: time to digital convert, high-precision, FPGA, carry chain, tap delay line