关键词: FPGA, HBM, DRAM, 高级可扩展接口, 双倍数据速率

Abstract: A multi-channel HBM2-PHY circuit is designed for high-speed and reliable data transmission between high-performance field programmable gate arrays (FPGA) and dynamic random access memory (DRAM). The circuit is designed using a 12 nm process to support up to eight independent channels and a data transfer rate of up to 1.6 Gbps. The FIFO cache is designed in the address and data paths of HBM2-PHY circuit to improve the data read and write efficiency. By designing adjustable delay chain circuit, the data sampling clock in high-speed receiving and transmitting circuit is adjusted, and the reliability of data transmission is improved. The simulation results show that the delay of the sampled clock signal can be adjusted by 512 steps, the delay time of each step is about 0.003 ns, and the integral nonlinearity (INL) is about 0.3 LSB. The eye view shows that the high-speed receiving and transmitting circuits perform well at a data rate of 1.6 Gbps.

Key words: field programmable gate array, high bandwidth memory, dynamic random access memory, advanced extensible interface, double data rate