关键词: FPGA, XADC, 温度检测, 分段补偿, 预警

Abstract: Research on the temperature detection technology of the on-chip Xilinx analog-to-digital converter (XADC) in field-programmable gate arrays (FPGAs) is of great significance for improving the reliability of chip overheating protection and early warning systems. Aiming at the problems of large detection errors and delayed early warning response in high and low temperature environments caused by the traditional full-temperature linear conversion compensation method inside FPGAs, this paper proposes an adaptive segmented compensation optimization method within high and low temperature ranges. In the temperature range of -10 ℃ to 30 ℃, the default linear conversion compensation is adopted; when the temperature is lower than -10 ℃ or higher than 30 ℃, targeted non-linear compensation is activated. The entire compensation process processes temperature data at the processing system (PS) end of the ZYNQ series FPGA chips (ultra-large-scale heterogeneous multi-core processors), giving full play to its fast processing speed and avoiding the occupation of programmable logic (PL) end resources to achieve efficient compensation. By constructing an early warning system architecture with collaborative work between the PS and PL ends, it is verified that under extreme high and low temperature working conditions, the temperature detection errors are reduced by approximately 80% and 70%, respectively, and the early warning can be triggered timely and effectively, demonstrating the reliability and practicability of the adaptive segmented compensation optimization method.

Key words: FPGA, XADC, temperature detection, segmented compensation, warning