关键词: 基本逻辑单元, 混合流装箱, 时序余量, FPGA

Abstract: For the whole circuit, all basic logic elements (BLEs) are interconnected through wire networks between them. Packing will change the connection method between the wire networks, and the connection method of different wire networks will correspond to different running time. The proposed mixed flow packing firstly implements the global optimal pairing for BLEs according to the hybrid first choice clustering, minimizing the delay on the critical path. Secondly, the threshold for balancing circuit timing and area is calculated according to the extreme deviation based on the maximum and minimum affinity values of paired BLEs. When the affinity value between BLEs is less than the threshold value, the “hill climbing” algorithm is used to ensure that the area is not too large. The timing calculation of the whole algorithm is done after the layout, which can obtain more accurate timing information, select a better critical path for packing, increase the timing slack, and reduce the final running time of the circuit.

Key words: basic logic element, mixed flow packing, timing slack, FPGA