关键词: JESD204B, 多通道, 高速, SiP

Abstract: Research on high-speed system-in-package (SiP) processing chips is of significant practical application value for the development of the modern high-speed data processing field. To address the common issues in current high-speed processing systems, such as a small number of channels, low integration, large occupied area, and high susceptibility to interference, a high-speed SiP processing chip scheme is proposed. This scheme takes the field-programmable gate array (FPGA) as the core, integrates 8-channel acquisition and 8-channel output, and supports the transmission of the standardized serial interface specified in the Joint Electron Device Engineering Council (JEDEC) Standard 204B (JESD204B). The internal analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) of the chip are all high-speed acquisition chips, which support the JESD204B interface protocol. The serializer rate can reach up to 10 Gbit/s, enabling fast data transmission and efficient signal processing. The architectural composition and performance parameters of this SiP processing chip are analyzed in depth. Practical measurements show that the package area is 20.25 cm², and the channel isolation is about 75 dB. Meanwhile, an architectural strategy with an external clock chip is proposed, which effectively improves the high-temperature resistance of the chip and further expands the application scenarios and applicable environments of similar high-speed SiP chips.

Key words: JESD204B, multi-channel, high-speed, SiP