[1] LANUZZA M, CORSONELLO P, PERRI S. Low-power level shifter for multi-supply voltage designs[J]. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2012, 59(12): 922-926. [2] 邹文英, 李晓蓉, 杨沛, 等. 端口双向耐高压电路的ESD防护设计技术[J]. 电子与封装, 2024, 24(1): 010301. [3] LUIS NUNEZ-YANEZ J, HOSSEINABADY M, BELDACHI A. Energy optimization in commercial FPGAs with voltage, frequency and logic scaling[J]. IEEE Transactions on Computers, 2016, 65(5): 1484-1493. [4] USAMI K, IGARASHI M, MINAMI F, et al. Automated low-power technique exploiting multiple supply voltages applied to a media processo[J]. IEEE Journal of Solid-State Circuits,1998,33(3): 463-472. [5] 季惠才, 陈珍海, 孙华, 等. 一种基于CMOS工艺的Gbps高速LVDS发送电路[J]. 电子与封装, 2009, 9(1): 24-27. [6] 吕江萍, 陈远金, 刘霞, 等. 集成电路中接口电路的可靠性设计[J]. 电子与封装, 2014, 14(3): 41-45. [7] SHARAFI M N, RASHIDIAN H, SHIRI N. A 38.5-fJ 14.4-ns robust and efficient subthreshold-to-suprathreshold voltage-level shifter comprising logic mismatch-activated current control circuit[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(6): 1906-1910. [8] 邱旻韡, 黄登华, 屈柯柯, 等. 兼容TTL电平的高速CMOS端口电路设计[J]. 电子与封装, 2023, 23(8): 080302. [9] VEENA M B, MADHURI R A, AISHWARYA S K, et al.. Design of Low Power Hybrid Level Shifter using MTCMOS[C]// 2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS), Bangalore, India, 2023: 292-297. [10] 周欢欢, 陈岚, 尹明会, 等. 基于40 nm CMOS工艺的电平转换器的设计及优化[J]. 半导体技术, 2015, 40(2): 93-96. [11] SABERI M, GHASEMZADEH Z, SCHMID A. A delay and power efficient voltage level shifter with low leakage power[C]// 2023 IEEE 36th International System-on-Chip Conference (SoCC), Santa Clara, CA, USA, 2023: 1-5. [12] LüTKEMEIER S, RüCKERT U. A subthreshold to above-threshold level shifter comprising a Wilson current mirror[J]. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2010, 57(9): 721-724. [13] LE V L, KIM T T. An area and energy efficient ultra-low voltage level shifter with pass transistor and reduced-swing output buffer in 65-nm CMOS[J]. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2018, 65(5): 607-611. [14] KIRAN P L, PRATHEEK K S, SATHVIKA M, et al. Current Mirror based Level Shifter aiding multitudinous conversion ranges[C]// 2024 International Conference on Integrated Circuits and Communication Systems (ICICACS), Raichur, India, 2024: 1-6. [15] 张春奇, 胡黎, 潘溯, 等. 一种高速、高共模噪声抗扰的电平位移电路[J]. 电子与封装, 2019, 19(6): 12-15. [16] CHU K M, PULFREY D L. A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic[J]. IEEE Journal of Solid-State Circuits, 1987, 22(4): 528-532. [17] CHANG I J, KIM J J, ROY K. Robust level converter design for sub-threshold logic[C]// Proceedings of the 2006 International Symposium on Low Power Electronics and Design - ISLPED '06, Tegernsee, Bavaria, Germany, 2006: 14. [18] SABERI M, SCHMID A. Analysis of power consumption and propagation delay in voltage level shifters[J]. IEEE Solid-State Circuits Letters, 2025, 8: 113-116. [19] KABIRPOUR S, JALALI M. A low-power and high-speed voltage level shifter based on a regulated cross-coupled pull-up network[J]. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2019, 66(6): 909-913. [20] LANUZZA M, CRUPI F, RAO S, et al. An ultralow-voltage energy-efficient level shifter[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2017, 64(1): 61-65. [21] KABIRPOUR S, JALALI M. A power-delay and area efficient voltage level shifter based on a reflected-output Wilson Current mirror level shifter[J]. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2020, 67(2): 250-254. [22] HOSSEINI S R, SABERI M, LOTFI R. A low-power subthreshold to above-threshold voltage level shifter[J]. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2014, 61(10): 753-757.
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