面向大算力应用的芯粒集成技术

doi:10.16257/j.cnki.1681-1070.2024.0107

电子与封装 ›› 2024, Vol. 24 ›› Issue (6): 060105 . doi: 10.16257/j.cnki.1681-1070.2024.0107

所属专题：硅通孔三维互连与集成技术

• “硅通孔三维互连与集成技术”专题 • 上一篇下一篇

面向大算力应用的芯粒集成技术

王成迁^1,2,汤文学¹,戴飞虎¹,丁荣峥¹,于大全²

1. 中国电子科技集团公司第五十八研究所，江苏无锡 214035；2. 厦门大学电子科学与技术学院，福建厦门 361005

收稿日期:2024-03-11 出版日期:2024-06-25 发布日期:2024-06-25
作者简介:王成迁（1987—），男，山东日照人，博士，高级工程师，主要研究方向为先进封装与微系统集成技术。

Chiplet Integration Technology for High Computing Power Application

WANG Chengqian^1,2, TANG Wenxue¹, DAI Feihu¹, DING Rongzheng¹, YU Daquan²

1. ChinaElectronics Technology Group Corporation No.58 Research Institute, Wuxi 214035, China; 2. School ofElectronic Science and Engineering, XiamenUniversity, Xiamen 361005, China

Received:2024-03-11 Online:2024-06-25 Published:2024-06-25

摘要/Abstract

摘要： 随着先进制程接近物理极限，摩尔定律已无法满足人工智能大算力需求。芯粒技术被公认为延续摩尔定律，提升芯片算力的最有效途径。针对芯粒技术研究热点，从集成芯片的应用与发展、典型芯粒封装技术、芯粒技术的挑战和机遇方面进行了系统性的梳理。详细列举了当前芯粒技术的应用成果，对比分析了2.5D、3D堆栈以及3D FO封装技术特点。

关键词: 大算力, 芯粒, 芯粒封装, 摩尔定律

Abstract: As advanced manufacturing processes approach physical limits, Moore's Law can no longer meet the demand for high computing power in artificial intelligence. Chiplet technology is widely recognized as the most effective method to continue Moore's Law and enhance chip computing power. In view of the research hotspots of Chiplet technology, the application and development of integrated chips, typical Chiplet packaging technology, challenges and opportunities of Chiplet technology are systematically reviewed. The current application achievements of Chiplet technology are detailed, and the characteristics of 2.5D, 3D stack, and 3D FO packaging technologies are compared and analyzed.

Key words: high computing power, Chiplet, Chiplet packaging, Moore's Law

中图分类号:

TN305.94

王成迁,汤文学,戴飞虎,丁荣峥,于大全. 面向大算力应用的芯粒集成技术[J]. 电子与封装, 2024, 24(6): 060105 .

WANG Chengqian, TANG Wenxue, DAI Feihu, DING Rongzheng, YU Daquan. Chiplet Integration Technology for High Computing Power Application[J]. Electronics & Packaging, 2024, 24(6): 060105 .

参考文献

[1] Open AI. AI and compute [EB/OL]. (2018-05-16) [2024-03-11]. https://openai.com/index/ai-and-compute/.
[2] 集成芯片前沿技术科学基础专家组，中国计算机学会集成电路专业委员会，中国计算机学会容错计算专业委员会. 中国计算机：集成芯片与芯粒技术白皮书 [EB/OL]. (2018-10-14) [2024-03-11]. https://www.sgpjbg.com/baogao/142807.html.
[3] MACK C A．Fifty years of Moore’s law[J]．IEEE Transactions on Semiconductor Manufacturing, 2011, 24(2): 202-207．
[4] MOORE G．Moore’s law[J]. Electronics Magazine, 1965, 38(8): 114．
[5] 吉勇, 王成迁, 李杨. 扇出型封装发展、挑战和机遇[J]. 电子与封装, 2020, 20(8): 080101.
[6] 陈龙, 黄乐天. 芯粒功能划分方法与互连体系综述[J]. 集成电路与嵌入式系统, 2024, 24(2): 41-49.
[7] SINGH T, RANGARAJAN S, JOHN D, et al. 2.1 Zen 2: The AMD 7 nm energy-efficient high-performance x86-64 microprocessor core[C]//2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2020.
[8] MA X H, WANG Y, WANG Y J, et al. Survey on Chiplets: Interface, interconnect and integration methodology[J]. CCF Transactions on High Performance Computing, 2022, 4(1): 43-52.
[9] ZHU H Z, JIAO B, ZHANG J S, et al. COMB-MCM: Computing-on-memory-boundary NN processor with bipolar bitwise sparsity optimization for scalable multi-Chiplet-module edge machine learning[C]//2022 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022.
[10] NAFFZIGER S, BECK N, BURD T, et al. Pioneering Chiplet technology and design for the AMD EPYC? and Ryzen? processor families: Industrial product[C]//2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), Valencia, Spain, 2021.
[11] XIA J, CHENG C N, ZHOU X P, et al. Kunpeng 920: The first 7-nm Chiplet-based 64-core ARM SoC for cloud services[J]. IEEE Micro, 2021, 41(5): 67-75.
[12] PAL S, LIU J Y, ALAM I, et al. Designing a 2048-Chiplet, 14336-core waferscale processor[C]//2021 58th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2021.
[13] 张双虎. 2024年: 芯粒“上车” 算力“破墙”[N]. 中国科学报, 2023-12-11(4).
[14] 项敏, 石磊, 强宏, 等. 浅析高性能封装技术的发展[J]. 微纳电子与智能制造, 2021，3(1): 82-88.
[15] 中投产业研究院. 2024—2028年中国芯粒（Chiplet）产业深度调研及投资前景预测报告[EB/OL]. (2024-02-21)[2024-03-11]. https://www.sohu.com/a/759052994_121822733.

中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

面向大算力应用的芯粒集成技术

Chiplet Integration Technology for High Computing Power Application

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 7

编辑推荐

Metrics

本文评价

[1]	何慧敏, 廖成意, 刘丰满, 戴风伟, 曹睿. 集成硅基转接板的PDN供电分析[J]. 电子与封装, 2024, 24(6): 60108-.
[2]	张爱兵, 李洋, 姚昕, 李轶楠, 梁梦楠. 基于硅通孔互连的芯粒集成技术研究进展[J]. 电子与封装, 2024, 24(6): 60110-.
[3]	黎科,张鑫硕,夏启飞,钟毅,于大全. 集成电路互连微纳米尺度硅通孔技术进展^*[J]. 电子与封装, 2024, 24(6): 60111-.
[4]	汤文学,孙莹,周立彦. Chiplet封装用有机基板的信号完整性设计[J]. 电子与封装, 2024, 24(2): 20101-.
[5]	解维坤, 蔡志匡, 刘小婷, 陈龙, 张凯虹, 王厚军. 芯粒测试技术综述[J]. 电子与封装, 2023, 23(11): 110101-.
[6]	吉勇，王成迁，李杨. 扇出型封装发展、挑战和机遇[J]. 电子与封装, 2020, 20(8): 80101-.
[7]	许居衍;黄安君. 后摩尔时代的技术创新[J]. 电子与封装, 2020, 20(12): 120101-.