关键词: 流水线ADC, 射频采样ADC, 低功耗, 无采样保持放大电路, 数字校准

Abstract: The paper presents a 12 bit 1 GS/s RF Sampling SHA-less Pipelined ADC, implemented on a 40 nm CMOS process. The proposed pipelined ADC employs switch capacitor voltage comparator (SC comparator)to handle the sampling networks mismatches at the input of the sub-ADC and the MDAC. Pre-charging reference voltagesrelaxesthe stress of comparatorsin backend sub-ADCs. To resolve 3.5 bit in its first stage and amplify the residue by factor of 4 relax the op-amp linearity, gain requirement, voltage swing in the first MDAC. Furthermore, using simple op-amp with high bandwidth and high linearity simplifies analog design and digital calibration. It achieves 11.2 bit ENOB, 70 dB SNR, 82 dB SFDR with a 455 MHz, 1.2 V full-scale input after calibration, while consuming 220 mW if digital calibration block is not considered.

Key words: pipelined ADC, RF sampling ADCs, low power, SHA-less, digital calibration