关键词: FPGA, 动态部分可重构, 分区算法

Abstract: At present, the dynamic partial reconfigurable design based on Field Programmable gate Array (FPGA) has become one of the hottest methods to realize hardware acceleration, but the partitioning method directly affects the area of reconfigurable regionsand reconfiguration time.Therefore, it is important to study the method of dividing the reconfigurable system into many reconfigurable modules (RMs) and allocating RMs toreconfigurable regions (RRs) on the FPGA.Based on the analysis and evaluation of the reconfiguration time and area utilization ratio of the existing partitioning technology, a new dynamic partial reconfigurable scheme is proposed.This method optimizes the partitioning process based on the graph clustering algorithm，thenthe optimal partitioning schemeis found automatically. Moreover,the dynamic connection between the reconfigurable regions is realized in the reconfiguration process. Finally,the area of reconfigurable regions and reconfiguration timeare optimized simultaneously.Compared with the Vipin algorithm scheme, the reconfiguration time of the proposed design is reduced by about 10%, and the area of reconfigurable regions is reduced by about 18.5%.

Key words: FPGA, dynamic partial reconfiguration, partitioning algorithm