关键词: DDR内存驱动, 跨导线性环, 快速瞬态响应

Abstract: In the paper,a design of LDO chip for DDR memory driver is described.The LDO uses translinear loop structure to increase the slew rate,making the LDO has a fast transient response.The upper and lower channels of the control loop do not match each other.One-sided Miller compensation is used to form the main pole and zero of the loop.Then the resistor R3 is introduced to form the compensation zero.The loop is represented as a single-pole system with good stability.The typical input voltage of the LDO is 1.2 V,the output voltage is 0.6 V,the load capacitance is 10 μF,with 1.5 A current sinking and sourcing ability,while integrating the 2.6A current limitability.This design meets the DDR memory application needs.The design is simulated by using 0.35 μm BCD process.The simulation results show that the design has good transient adjustment ability and stability.

Key words: DDR memory driver, translinear loop, fast transient response