中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2018, Vol. 18 ›› Issue (10): 13 -16. doi: 10.16257/j.cnki.1681-1070.2018.0108

• 封装、组装与测试 • 上一篇    下一篇

一种优化FPGA测试配置时间的方法

肖艳梅1 ,陆 锋12   

  1. 1.江南大学物联网工程学院,江苏 无锡 214122; 2.中国电子科技集团公司第五十八研究所,江苏 无锡 214072
  • 收稿日期:2018-06-11 出版日期:2018-10-20 发布日期:2018-10-20
  • 作者简介:肖艳梅(1994—),女,安徽人,目前就读于江南大学集成电路工程专业,硕士研究生,同时在中国电子科技集团公司第五十八研究所从事集成电路测试工作,主要研究方向为数字集成电路测试。

A Method to Optimize the Configuration Time of FPGA Test

XIAO Yanmei, LU Feng   

  1. 1. School of Internet of Things, Jiangnan University, Wuxi 214122, China; 2. China Electronics Technology Group Corporation No.58 Research Institute, Wuxi 214072, China
  • Received:2018-06-11 Online:2018-10-20 Published:2018-10-20

摘要: 随着现场可编程门阵列(FPGA)规模发展到千万门级以上,配置向量越来越大,超过95%的FPGA制造测试时间用于加载测试配置比特流。为实现FPGA的快速配置测试,提出了一种FPGA快速测试配置及实现方法。采用V93000测试系统,通过在一个周期内加载4行配置向量对电路配置比特流的测试时间进行优化(即4X配置方式)。以Xilinx公司Virtex-7系列FPGA-XC7VX485T为例进行了测试验证。测试数据表明,与一般配置方法相比,4X配置方式下FPGA单次配置时间减少了74.1%,解决了FPGA测试中数据配置与测试时间的矛盾。

关键词: ATE, FPGA, 4X配置方式, 在系统快速配置

Abstract: As the field programmable gate array (FPGA) scales to more than 10 million gates, the depth of the configuration vector is getting larger and larger, and over 95% of the FPGA manufacturing test time is used to load the test configuration bit stream. In order to realize the fast configuration test of FPGA, a quick test configuration and implementation method of FPGA is proposed. Using the V93000 test system, the test time of the circuit configuration bit stream is optimized by loading 4 rows of configuration vectors in one cycle (is 4X configuration).The Xilinx Virtex-7 series FPGA-XC7VX485T was used as an example to verify the test. The test data shows that compared with the general configuration method, the FPGA single configuration time is reduced by 74.1% in the 4X configuration mode, which solves the contradiction between data configuration and test time in the FPGA test.

Key words: automated test equipment, FPGA, 4X configuration, rapid system configuration

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