关键词: 自动提取, 算法, ECC, DDR, 后门访问, SystemVerilog

Abstract: When the double data rate (DDR) control system turns on error checking and correcting (ECC) function, if the accessed data width is less than the total data width of DDR memory in simulation, the initial data in DDR memory should be initialized with ECC value. Otherwise, simulation can’t work properly. The traditional method is to initialize the data through the front door access, but this method will consume a lot of time. In order to reduce the simulation time to initialize data and achieve the same purpose of verification, this paper presents a DDR back door access verification method which can identify configuration information and calculate ECC value automatically. In this method, the configuration file and data file are established, and then the System Verilog language is used to code the processing file which can extract related information automatically, the processing file using System Verilog language implements the same ECC algorithm as the DDR controller’s (Verilog implements), then data’s ECC value is calculated by algorithm automatically. Finally, the data and ECC values are load into DDR using back door method. The results show that the simulation goes into an endless loop when the ECC data are not initialized, but after initializing a small address range, the proposed method can reduce time about 15.2% compared with the front door method, and the same verification purpose is achieved. It can be inferred that if the initialization address range is expanded to the order of magnitude of kB, MB, GB, hours or even more time can be reduced. The present method is suitable for all types of DDR system.

Key words: extractautomatically, algorithm, ECC, DDR, backdooraccess, SystemVerilog