晶圆级封装中的垂直互连结构

doi:10.16257/j.cnki.1681-1070.2021.1007

电子与封装 ›› 2021, Vol. 21 ›› Issue (10): 100107 . doi: 10.16257/j.cnki.1681-1070.2021.1007

所属专题：微系统与先进封装技术；封装技术

• “微系统与先进封装技术”专题 • 上一篇下一篇

晶圆级封装中的垂直互连结构

徐罕¹;朱亚军¹;戴飞虎¹;高娜燕¹;吉勇¹;王成迁^1,2

1. 中国电子科技集团公司第五十八研究所，江苏无锡　214072；2. 厦门大学电子科学与技术学院，福建厦门　361005

收稿日期:2020-12-07 出版日期:2021-10-26 发布日期:2021-06-19
作者简介:徐罕（1989—），男，江苏淮安人，本科，工程师，目前主要从事晶圆级先进封装研究相关工作。

The Vertical Interconnection Structures ofWafer Level Package

XU Han¹, ZHU Yajun¹, DAI Feihu¹, GAO Nayan¹, JI Yong¹, WANG Chengqian^1,2

1. China ElectronicsTechnology Group Corporation No.58Research Institute, Wuxi 214072, China; 2. School of Electronic Science and Engineering, Xiamen University, Xiamen 361005, China

Received:2020-12-07 Online:2021-10-26 Published:2021-06-19

摘要/Abstract

摘要： 随着电子产品需求的不断提升，半导体封装技术的发展已经从2D结构发展到2.5D乃至3D结构，这对包括高密度集成和异质结构封装在内的系统级封装（System in Packaging，SiP）提出了更高的要求。以当下热门的晶圆级封装为切入点，重点阐述并总结目前在晶圆级封装结构中出现的3种垂直互连结构：硅通孔（Through Silicon Via，TSV)、塑封通孔(Through Molding Via，TMV)、玻璃通孔(Through Glass Via，TGV)。这3种垂直互连结构也是业内公认的推进三维集成封装的关键技术。从3种垂直互连结构的发展历史、工艺方法和应用领域等多个方面进行提炼总结，明确垂直互连结构的现状能力及未来挑战，为晶圆级三维集成封装技术开发和探索提供参考。

关键词: 晶圆级封装, 垂直互连, TSV, TMV, TGV

Abstract: Along with the continuous improvement of product applications and market demands for many years，the development of semiconductor packaging technology has developed from 2D to 2.5D and even to 3D integrated structure. It puts forward higher requirements for SiP (system in packaging), including high density integration and heterogeneous structure packaging. Three kinds of vertical interconnection structures in wafer level packaging are mainly expounded and summarized： TSV (through silicon via), TMV (through mold via) and TGV (through glass via). Three structures are also considered as the key technologies to promote 3D integrated SiP packaging in the industry. Three vertical interconnect structures will be summarized from the development history, process methods and application fields, the current capabilities and future challenges of vertical interconnect structures will be clarified, and three structures will provide reference for the technological development and exploration of wafer level integrated packaging.

Key words: waferlevelpackaging, verticalinterconnection, TSV, TMV, TGV

中图分类号:

TN305.94

徐罕, 朱亚军, 戴飞虎, 高娜燕, 吉勇, 王成迁. 晶圆级封装中的垂直互连结构[J]. 电子与封装, 2021, 21(10): 100107 .

XU Han, ZHU Yajun, DAI Feihu, GAO Nayan, JI Yong, WANG Chengqian. The Vertical Interconnection Structures ofWafer Level Package[J]. Electronics & Packaging, 2021, 21(10): 100107 .

参考文献

[1] LAU J H. Evolution and outlook of TSV and 3D IC/Si integration[C]. 2010 12th Electronics Packaging Technology Conference. IEEE, 2010: 560-570.
[2] SMITH M G, EMANUEL S. Methods of making thru-connections in semiconductor wafers:U.S.Patent 3,343,256[P]. 1967-9-26.
[3] VAN O J, MERCHA A, KATTI G, et al. 3D stacked IC demonstration using a through silicon via first approach[C]. 2008 IEEE International Electron Devices Meeting.2008:1-4.
[4] REDOLFI A, VELENIS D, THANGARAJU S, et al. Implementation of an industry compliant, 5×50 μm，via-middle TSV technology on 300mm wafers[C]. 2011 IEEE 61st Electronic Components and Technology Conference (ECTC). 2011: 1384-1388.
[5] VAN H S, STUCCHI M, LI Y, et al. Small pitch, high aspect ratio via-last TSV module[C]// 2016 IEEE 66th Electronic Components and Technology Conference (ECTC). 2016: 43-49.
[6] AOKI M, FURUTA F, HOZAWA K, et al. Fabricating 3D integrated CMOS devices by using wafer stacking and via-last TSV technologies[C]. 2013 IEEE International Electron Devices Meeting.IEEE, 2013: 29.5.1-29.5.4.
[7] ELOY J. Market Trends for 3D Stacking[Z]. EMC 3D, 2007.
[8] 童志义. 3DIC集成与硅通孔(TSV)互连[J]. 电子工业专用设备,2 009(3): 27-34.
[9] BRAUN T, et al. Through mold via technology for multi-sensor stacking[C]. 2012 IEEE 14th Electronic Packaging Technology Conference.2012:316-321.
[10] KIM J, et al. Application of through mold via (TMV) as PoP base package[C]. 2008 58th Electronic Components and Technology Conference. Lake Buena Vista, FL, USA. 2008: 1089-1092.
[11] YOSHIDA A, et al. A study on an Ultra Thin PoP using through mold via technology[C]// 2011 IEEE 61st Electronic Components and Technology Conference (ECTC). Lake Buena Vista, Florida, USA.2011: 1547-1551.
[12] HSU H C, et al.Reliability design and optimization process on through mold via using ultrafast laser[J]. Polymers and Polymer Composites, 2018, 26(1): 1-8.
[13] LIN Y, et al. Advanced 3D eWLB-PoP (embedded wafer level ball grid array-package on package) technology[C]. 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).2016.
[14] PARK S H, PARK J Y, KIM Y H. Effect of permanganate treatment on through mold vias for an embedded wafer level package[J]. Electronic Materials Letters, 2013, 9(4): 459-462.
[15] HSU H, et al. Through Mold Via (TMV) by gas-aided laser[C]. 2016 International Conference on Electronics Packaging (ICEP). 2016.
[16] TOPPER M, et al.3-D Thin film interposer based on TGV (Through Glass Vias): An alternative to Si-interposer[C]// 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC). Las Vegas, NV, 2010: 66-73.
[17] CHEN L, YU T, REN X, et al. Development of low cost through glass via (TGV) interposer with high-Q inductor and MIM capacitor[C]// 2020 21st International Conference on Electronic Packaging Technology (ICEPT). Guangzhou, China, 2020: 1-4.
[18] HWANGBO S,YOON Y,SHOREY A. Glass interposer integrated dual-band millimeter wave TGV antenna for inter-/intra chip and board communications[C]// 2016 IEEE International Symposium on Antennas and Propagation (APSURSI).Fajardo, 2016: 1639-1640.
[19] CHANG Y,et al.A novel fabrication process and measurement results of a 28GHz glass antenna with single TGV for 5G communication applications[C]// 2019 14th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT). Taipei, Taiwan, 2019: 112-115.
[20] KROHNERT K, FRIEDRICH G, STERUKHIN D, et al. Reliability of Through Glass Vias and hermetically sealing for a versatile sensor platform[C]// 2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC).T?nsberg, estfold, Norway, 2020: 1-6.
[21] OSTHOLT R, AMBROSIUS N, KRUGER R A. High speed through glass via manufacturing technology for interposer[C]. Proceedings of the 5th Electronics System-integration Technology Conference (ESTC).Helsinki, 2014: 1-3.
[22] CHEN L, WU H, ZHANG M, et al. Development of Laser-Induced Deep Etching Process for Through Glass Via[C]// 2019 20th International Conference on Electronic Packaging Technology(ICEPT). Hong Kong, China, 2019: 1-4.
[23] KURAMOCHI S, KUDO H, AKAZAWA M, et al. Glass interposer technology advances for high density packaging[C]// 2016 IEEE CPMT Symposium Japan (ICSJ). Kyoto, 2016: 213-216.
[24] 陈力,杨晓锋,于大全.玻璃通孔技术研究进展[J]. 电子与封装,2021, 21(4): 040101.

中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

晶圆级封装中的垂直互连结构

The Vertical Interconnection Structures ofWafer Level Package

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 15

编辑推荐

Metrics

本文评价

[1]	孙莹;周立彦;王剑峰;许吉;明雪飞;王波. 基于晶圆级封装PDK的微带发夹型滤波器设计[J]. 电子与封装, 2024, 24(8): 80202-.
[2]	张旋,李海娟,吴道伟,张雷. 2.5D TSV转接板无损检测方法的研究[J]. 电子与封装, 2024, 24(6): 60102-.
[3]	许增光, 李哲, 钟诚, 刘志权. TSV电镀过程中Cu生长机理的数值模拟研究进展^*[J]. 电子与封装, 2024, 24(6): 60104-.
[4]	黎科,张鑫硕,夏启飞,钟毅,于大全. 集成电路互连微纳米尺度硅通孔技术进展^*[J]. 电子与封装, 2024, 24(6): 60111-.
[5]	王刚, 赵心然, 尹宇航, 夏晨辉, 周超杰, 袁渊, 王成迁. 基于分形结构的天线设计及天线-芯片一体化射频组件制造工艺[J]. 电子与封装, 2023, 23(8): 80402-.
[6]	陈晨;尹春燕;夏晨辉;尹宇航;周超杰;王刚;明雪飞. 垂直互联结构的封装天线技术研究[J]. 电子与封装, 2023, 23(7): 70205-.
[7]	王方成, 刘强, 李金辉, 叶振文, 黄明起, 张国平, 孙蓉. 临时键合技术在晶圆级封装领域的研究进展^*[J]. 电子与封装, 2023, 23(3): 30104-.
[8]	申九林, 马书英, 郑凤霞, 王姣, 魏浩. 基于硅基扇出（eSiFO^®）技术的先进指纹传感器晶圆级封装工艺开发[J]. 电子与封装, 2023, 23(3): 30111-.
[9]	解维坤, 蔡志匡, 刘小婷, 陈龙, 张凯虹, 王厚军. 芯粒测试技术综述[J]. 电子与封装, 2023, 23(11): 110101-.
[10]	梁亨茂. 基于晶圆键合的MEMS圆片级封装研究综述^*[J]. 电子与封装, 2022, 22(12): 120201-.
[11]	刘骁知;曾小平;冉万宁;丁杰;周佳明. 一种基于扇出晶圆级封装技术的控制模块设计[J]. 电子与封装, 2021, 21(8): 80202-.
[12]	谢迪;李浩;王从香;崔凯;胡永芳. 基于TGV工艺的三维集成封装技术研究[J]. 电子与封装, 2021, 21(7): 70203-.
[13]	张振越;夏鹏程;王成迁;蒋玉齐. 扇出型晶圆级封装中圆片翘曲研究[J]. 电子与封装, 2021, 21(4): 40203-.
[14]	李胜利;马占锋;高健飞;王春水;黄立. MEMS晶圆级封装种子层刻蚀工艺研究[J]. 电子与封装, 2021, 21(11): 110201-.
[15]	马书英, 王姣, 刘轶, 郑凤霞, 刘玉蓉, 肖智轶. 浅析CMOS图像传感器晶圆级封装技术[J]. 电子与封装, 2021, 21(10): 100108-.