关键词: 系统级封装, 双倍速率同步动态随机存储器, 信号完整性, 阻抗补偿, 系统级仿真

Abstract: With the continuous improvement of data transmission rates of DDR interfaces, the signal integrity (SI) problems faced by system-in-package (SiP) memory channels have become increasingly prominent. Traditional integrated modeling methods struggle to balance simulation efficiency and accuracy, and are often disconnected from the actual development board environment. This paper proposes a method based on modular S-parameter extraction and system-level co-simulation. First, the SiP package substrate with the redistribution layer (RDL) removed and the RDL itself are decoupled, and their S-parameters are extracted independently. During this process, port reference impedances are set in segments according to the substrate impedance compensation design to improve model accuracy. Subsequently, the modularly combined package model is integrated with the controller, DDR devices, and development board interconnect transmission line models for system-level co-simulation. The results show that this method can more accurately predict the signal performance of SiP devices on real development boards while improving simulation efficiency, providing a reliable basis for the early design optimization of SiP-packaged DDR chips.

Key words: system-in-package, double-rate synchronous dynamic random-access memory, signal integrity, impedance compensation, system-level simulation