关键词: JESD204B协议, 高速串行接口, 接收端电路, 数模转换器

Abstract: An interface circuit for 4-channel, 16 bit, 2.5 GSa/s digital to analog converter is designed. The single channel uses a 4-channel parallel transmission method to reduce the design difficulty of the circuit and implement the data link layer and transport layer of the protocol through link establishment, data processing, error statistics and module deframer. A universal verification methodology platform is built to interact with the designed receiver circuit to improve the verification efficiency. Based on a 65 nm process library, the logic synthesis and layout design of the circuit are carried out. The test results after the chip is taped out show that the function of the receiver circuit meets the requirements of JESD204B protocol, and the single channel data transmission rate can reach up to 12.5 Gbit/s.

Key words: JESD204B protocol, high speed serial interface, receiver circuit, digital to analog converter