关键词: 先进封装, 圆台硅通孔, 等离子刻蚀法

Abstract: It becomes more and more difficult to maintain Moore's law in the manufacturing stage of integrated circuits, and the use of three-dimensional space in the packaging stage can be regarded as an extension of Moore's law. Silicon via is a common technology to realize advanced packaging by using three-dimensional space. In the existing technology, the circular truncated cone through silicon via applied to the packaging of CMOS image sensor devices is realized by continuous transverse etching on the top, which is hard to improve the packaging density and has certain requirements for the resolution of lithography equipment. Aiming at the problems in the existing technology, a circular truncated cone through silicon via hole with strict controlled transverse etching (undercut size is 3%-12% of the critical dimension) has been studied and explored. By adjusting the power of the lower electrode (not more than 30 W is required), this method can obtain a circular truncated cone through silicon via hole with adjustable side wall angle (70°-88°) and the size of the through-hole bottom opening smaller than the defined characteristic size of lithography. This method is expected to be extended to three-dimensional integrated circuits, which will help to maintain Moore's law in the packaging stage.

Key words: advanced packaging, circular truncated conethrough silicon via, plasma etch method