关键词: 晶圆级封装, 扇出, eSiFO^?, 指纹传感器, 高可靠性

Abstract: The conventional wafer level chip scale package (WLCSP) is a standard fan-in package structure. With the increase of the number of I/O, it cannot provide enough space for the placement of redistribution layer (RDL). it cannot provide enough space for the placement of redistribution layer (RDL). In recent years, the embedded packaging technologyof fan-out area around chip has been developed, which has the advantages of high I/O number, low cost, flexible integration, and small package size. Fan-out wafer-level packaging (FOWLP) uses epoxy molding compound (EMC), which faces many technical problems such as wafer warpage, coefficient of thermal expansion (CTE) mismatch between different materials in each layer and high cost. A brand-new wafer-level embedded silicon fan-out (eSiFO^®) package technology is reported and it is appliedto the package of capacitive fingerprint sensor chips. In this innovative integrated device packaging process, the ASIC chip of 5.6 mm×1.0 mm size is thinned to 90 μm, and then embedded into the silicon cavities to form a reconstructed wafer.During the whole process, the metal coverage area is more than 80%, but the warpage of the wafer is less than 2 mm. Ten masks are used in the entire wafer-level packaging process, and the product yield reaches 98%.The product has passed standard reliability tests including pre-con testing, temperature cycle (TCT) testing, high accelerated temperature, and humidity stress test (u-HAST) and high temperature storage test (HTST).

Key words: wafer level packaging, fan-out, eSiFO^?, fingerprint sensor, high reliability