[1] MUNOZ R. Managing trade-offs in the chiplet era [J]. Chip Scale Review, 2022, 26(1): 30-34. [2] 蒋剑飞, 王琴, 贺光辉, 等. Chiplet技术研究与展望[J]. 微电子学与计算机, 2022, 39(1): 1-6. [3] LIN P Y, YEW M C, YEH S S, et al. Reliability performance of advanced organic interposer (CoWoS?-R) packages[C]//2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021: 723-728. [4]MAHAJAN R, SANKMAN R, PATEL N, et al. Embedded multi-die interconnect bridge (EMIB): A high density, high bandwidth packaging interconnect[C]// Electronic Components & Technology Conference. May 31-June 3, 2016, Las Vegas, Nevada, USA. IEEE, 2016: 557-565. [5] PRASAD C, CHUGH S, GREVE H, et al. Silicon reliability characterization of Intel's Foveros 3D integration technology for logic-on-logic die stacking[C]// 2020 IEEE International Reliability Physics Symposium (IRPS), April 28-May 30, 2020. Dallas, USA. IEEE, 2020. [6]Yole. High-end performance packaging 2022 – Focus on 2.5D/3D Integration[Z/OL]. (2022-03-01)[2023-02-20]. https://www.yolegroup.com/product. [7] CLARK D. Semiconductor packaging trends: An OSAT perspective [J]. Chip Scale Review, 2022, 26(1): 6-9. [8] HUANG P K, LU C Y, WEI W H, et al. Wafer level system integration of the fifth generation CoWoS?-S with high performance Si interposer at 2500 mm2[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021: 101-104. [9]HWANG Y, MOON S, NAM S, et al. Chiplet-based system PSI optimization for 2.5D/3D advanced packaging implementation[C]// 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), May 31-June 4, 2022, San Diego, USA. IEEE, 2022: 12-17. [10] LEE L C T, CHANG Y, HUANG S, et al. Advanced HDFO packaging solutions for chiplets integration in HPC application[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021: 8-13. [11] HU D C, CHEN E H, LEE J C, et al. 2.2D die last integrated substrate for high performance applications[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021: 157-163. [12]GAO G L, MIRKARIMI L, FOUNTAIN G, et al. Die to wafer hybrid bonding for chiplet and heterogeneous integration: Die size effects evaluation-small die applications[C]// 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), May 31-June 4, 2022, San Diego, USA. IEEE, 2022: 1975-1981. [13] RUDOLPH C, HANISCH A, VOIGTL?NDER M, et al. Enabling D2W/D2D hybrid bonding on manufacturing equipment based on simulated process parameters[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021:40-44. [14] IEEE. Heterogeneous integration roadmap[Z/OL].[2023-02-20]. https://eps.ieee.org/images/files/HIR_2021/ch02_hpc. [15] DAS SHARMA D, PASDAST G, QIAN Z G, et al. Universal chiplet interconnect express (UCIe): An open industry standard for innovations with chiplets at package level[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2022, 12(9): 1423-1431. [16] 吴优. 中国Chiplet技术标准发布,超60家企业参与编制[Z/OL] . (2022-12-20) [2023-02-20].https://www.leiphone.com/category/chips/4hqx1mHF20yyPnh8.html. [17] LI Y, GOYAL D. 3D microelectronic packaging[M]. Switzerland: Springer Nature, 2017: 380-397. [18] TUMMALA R, SWAMINATHAN M, NIMBALKAR P. A new and historic packaging era[J]. Chip Scale Review, 2022, 26(2): 6-10. [19] SIANG LIM S P, CHONG S C, CHIDAMBARAM V. Comprehensive study on chip to wafer hybrid bonding process for fine pitch high density heterogeneous applications[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021:438-444. [20] CHONG S C, LIM S S B, SEIT W W, et al. Comprehensive study of thermal impact on warpage behavior of FOWLP with different die to mold ratio[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021:1082-1087. [21] KESER B, KR?HNERT S. Advances in embedded and fan-out wafer-level packaging technologies[M].Hoboken: John Wiley & Sons Inc., 2019:117-140. [22] KIM Y, JEON Y Y, LEE S Y, et al. Fine RDL patterning technology for heterogeneous packages in fan-out panel level packaging[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021: 717-722. [23] GERBER M, CAO L H, GUPTA V, et al. Vertically-integrated packaging solutions driven by innovations[J]. Chip Scale Review, 2022, 26(4): 12-21. [24] CHERY E, SLABBEKOORN J, PINHO N, et al. Advances in photosensitive polymer based damascene RDL process: Toward submicrometer pitches with more metal layers[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021: 340-346. [25]SUK K L, LEE S H, KIM J Y, et al. Low cost Si-less RDL interposer package for high performance computing applications[C]// 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), May 29-June 1, 2018, San Diego, USA. IEEE, 2018: 64-69. [26] CHIANG Y P, TAI S P, WU W C, et al. InFO-_oS (integrated fan-out on substrate) technology for advanced chiplet integration[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021: 130-135. [27] LAU J H. Bridges for chiplet design and heterogeneous integration packaging[J]. Chip Scale Review, 2022, 26(1): 21-28. [28] Ian Cutress. 3D fabric: The home for TSMC’s 2.5D and 3D stacking roadmap [Z/OL]. (2020-09-02) [2023-02-20]. https://www.anandtech.com/show/16051/3dfabric-the-home-for-tsmc-2-5d-and-3d-stacking-roadmap. [29]KUDO H, TAKANO T, AKAZAWA M, et al. High-speed, high-density and highly-manufacturable Cu-filled through-glass-via channel (Cu bridge) for multi-chiplet systems[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021: 1031-1037. [30] SWAMINATHAN M, RAVICHANDRAN S. Heterogeneous integration for AI applications: Status and future needs (part2) [J]. Chip Scale Review, 2022, 26(2): 35-45. [31] NAM S, KIM Y, JANG A, et al. The extremely large 2.5D molded interposer on substrate (MIoS) package integration-warpage and reliability[C]//2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021: 1998-2002. [32]LIN V, LAI D, WANG Y P. The optimal solution of fan-out embedded bridge (FO-EB) package evaluation during the process and reliability test[C]// 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), May 31-June 4, 2022, San Diego, USA. IEEE, 2022: 1080-1084. [33] LAU J H, KO C T, PENG C Y, et al. Reliability of chip-last fan-out panel-level packaging for heterogeneous integration[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021: 359-364. [34] LIN Y M, ZHAN C J, JUANG J Y, et al. Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking[C]// 2011 Electronic Components and Technology Conference, May 31-June 3, 2011, Lake Buena Vista, USA. IEEE, 2011: 351-357. [35] YOU H Y, KIM B J, JOO Y C. Electromigration behavior of micro Sn bump under pulsed DC[C]// IEEE CFP09RPS-CDR 47th Annual International Reliability Physics Symposium, April 26-30, 2009, Montreal, Canada. IEEE, 2009: 143-148. [36] KUDO H, TAKANO T, SAKAMOTO K, et al. Effectiveness of inorganic dielectric layer on submicron-scale Cu traces against thermal oxidative stress[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021: 353-358. [37] LEE D W, MAYBERRY R, MACKIE A, et al. Optimizing reflowed solder TIM (sTIMs) processes for emerging heterogeneous integrated packages[C]// 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), May 31-June 4, 2022, San Diego, USA. IEEE, 2022: 1228-1237. [38] ROY R, DAS S, LABBE B, et al. Co-design of thermal management with system architecture and power management for 3D ICs[C]// 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), May 31-June 4, 2022, San Diego, USA. IEEE, 2022: 211-220. [39] LIN P Y, KUO S L, YAN K, et al. Advanced thermal integration for HPC packages with two-phase immersion cooling[C]// 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), May 31-June 4, 2022, San Diego, USA. IEEE, 2022: 566-573. [40] HUNG J N, LI H C, LIN P F, et al. Advanced system integration for high performance computing with liquid cooling[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021: 105-111. [41] KIM Y, BAE J, JUNG H, et al. Metal thermal interface material for the next generation FCBGA[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021: 613-618. [42] HUANG Y L, CHUNG C K, LIN C F, et al. Highly thermal dissipation for large HPC package using liquid metal materials[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021: 1102-1108. [43]SU P J, LIN D, LIN S E, et al. High thermal graphite TIM solution applied to fan-out platform[C]// 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), May 31-June 4, 2022, San Diego, USA. IEEE, 2022: 1224-1227. [44] SEO S K, JO C, CHOI M, et al. CoW package solution for improving thermal characteristic of TSV-SiP for AI-inference[C]//2021 IEEE 71st Electronic Components and Technology Conference (ECTC), June 1-July 4, 2021, San Diego, USA. IEEE, 2021: 1115-1118.
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