芯粒互连测试向量生成与测试方法研究

doi:10.16257/j.cnki.1681-1070.2024.0175

电子与封装 ›› 2024, Vol. 24 ›› Issue (11): 110103 . doi: 10.16257/j.cnki.1681-1070.2024.0175

• ICTC2024（集成电路测试大会）专题 • 上一篇下一篇

芯粒互连测试向量生成与测试方法研究

解维坤^1,2，李羽晴²，殷誉嘉²，王厚军¹

1. 电子科技大学自动化工程学院，成都? 611731；2. 中国电子科技集团公司第五十八研究所，江苏无锡? 214035

收稿日期:2024-10-23 出版日期:2024-11-25 发布日期:2024-11-25
作者简介:解维坤（1980—），男，山东青岛人，博士研究生，研究员，主要研究方向为FPGA等可编程器件测试技术、芯粒可测性设计与测试技术。

Research on Vector Generation and Testing Method for Chiplet Interconnection Testing

XIE Weikun^1,2, LI Yuqing², YIN Yujia², WANG Houjun¹

1. School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China; 2. China Electronics Technology GroupCorporation No.58 Research Institute, Wuxi 214035, China

Received:2024-10-23 Online:2024-11-25 Published:2024-11-25

摘要/Abstract

摘要： 基于芯粒的2.5D和3D集成系统产品都具有大量的芯粒间互连，不可避免地会出现各种制造缺陷，互连测试对于提高2.5D和3D集成系统产品大规模生产过程中的质量和产量至关重要。在研究传统的I-ATPG和真/补测试算法等互连测试方法的基础上提出了一种新的代码字编码方法，只需要4个代码字即可对所有矩形网络和六角网络进行代码字编码。设计了一种基于IEEE1838标准的芯粒集成系统测试架构，给出了一种典型的双芯粒互连电路并进行了测试和仿真验证，系统性地介绍了芯粒间互连测试技术。

关键词: 芯粒, 互连测试, 可测性设计

Abstract: Both 2.5D and 3D integrated system products based on Chiplet have a large number of Chiplet interconnections, which inevitably lead to various manufacturing defects. Interconnection testing is crucial to improving the quality and yield of 2.5D and 3D integrated system products during large-scale production. Based on the study of traditional interconnection testing methods such as I-ATPG and true/complement testing algorithm, a new code word encoding method is proposed, which only requires 4 code words to encode all rectangular and hexagonal networks. A test architecture of Chiplet integrated system based on IEEE1838 standard is designed, and a typical dual-Chiplet interconnection circuit is presented and tested and verified by simulation, so as to systematically introduce Chiplet interconnection testing technology.

Key words: Chiplet, interconnection testing, design for testability

中图分类号:

TN407

解维坤，李羽晴，殷誉嘉，王厚军. 芯粒互连测试向量生成与测试方法研究[J]. 电子与封装, 2024, 24(11): 110103 .

XIE Weikun, LI Yuqing, YIN Yujia, WANG Houjun. Research on Vector Generation and Testing Method for Chiplet Interconnection Testing[J]. Electronics & Packaging, 2024, 24(11): 110103 .

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中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

芯粒互连测试向量生成与测试方法研究

Research on Vector Generation and Testing Method for Chiplet Interconnection Testing

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