中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2023, Vol. 23 ›› Issue (3): 030102 . doi: 10.16257/j.cnki.1681-1070.2023.0041

所属专题: 先进三维封装与异质集成

• “先进三维封装与异质集成”专题 • 上一篇    下一篇

芯片三维互连技术及异质集成研究进展*

钟毅1;江小帆1;喻甜1;李威1,2;于大全1,2   

  1. 1. 厦门大学电子科学与技术学院,福建 厦门 361005;2. 厦门云天半导体科技有限公司,福建 厦门 361013
  • 收稿日期:2022-11-01 出版日期:2023-03-24 发布日期:2023-01-12
  • 作者简介:钟毅(1991—),男,江西赣州人,博士,助理教授,主要研究方向为高密度互连、传感器封装、电子封装可靠性等。

Advances in Three-DimensionInterconnection Technology and Heterogeneous Integration of Chips

ZHONG Yi1, JIANG Xiaofan1, YU Tian1, LI Wei1,2, YU Daquan1,2   

  1. 1.School of Electronic Science and Engineering, Xiamen University, Xiamen361005, China;2.Xiamen Sky Semiconductor Technology Co., Ltd., Xiamen 361013, China
  • Received:2022-11-01 Online:2023-03-24 Published:2023-01-12

摘要: 集成电路的纳米制程工艺逐渐逼近物理极限,通过异质集成来延续和拓展摩尔定律的重要性日趋凸显。异质集成以需求为导向,将分立的处理器、存储器和传感器等不同尺寸、功能和类型的芯片,在三维方向上实现灵活的模块化整合与系统集成。异质集成芯片在垂直方向上的信号互连依赖硅通孔(TSV)或玻璃通孔(TGV)等技术实现,而在水平方向上可通过再布线层(RDL)技术实现高密度互连。异质集成技术开发与整合的关键在于融合实现多尺度、多维度的芯片互连,通过三维互连技术配合,将不同功能的芯粒异质集成到一个封装体中,从而提高带宽和电源效率并减小延迟,为高性能计算、人工智能和智慧终端等提供小尺寸、高性能的芯片。通过综述硅通孔、玻璃通孔、再布线层技术及相应的2.5D、3D异质集成方案,阐述了当前研究现状,并探讨存在的技术难点及未来发展趋势。

关键词: 三维异质集成, 先进封装, 硅通孔, 玻璃通孔, 再布线层

Abstract: As the nano fabrication process of integrated circuits is approaching its physical limit gradually, it is becoming increasingly important to continue and expand Moore's Law through heterogeneous integration. Heterogeneous integration is demand-oriented, realizing flexible modular integration and system integration in three-dimensional direction for chips of different sizes, functions and types, such as discrete processors, memories and sensors. Heterogeneous integrated chips rely on either through silicon via (TSV) or through glass via (TGV) technologies for signal interconnection in the vertical direction. In horizontal direction, high density interconnection can be achieved through redistribution layer (RDL) technology. Through the cooperation of three-dimensional interconnection technology, the chiplets with different functions are heterogeneous integrated into one package, so as to improve the bandwidth and power efficiency and reduce delay, and provide small and high-performance chips for high-performance computing, artificial intelligence and intelligent terminals. The technology of TSV, TGV and RDL, and the corresponding 2.5D, 3D heterogeneous integration schemes are reviewed. The current research status is described. The existing technical difficulties and future development trend is discussed.

Key words: three-dimension integration, advanced packaging, through silicon via, through glass via, redistribution layer

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