芯粒测试技术综述

doi:10.16257/j.cnki.1681-1070.2023.0170

电子与封装 ›› 2023, Vol. 23 ›› Issue (11): 110101 . doi: 10.16257/j.cnki.1681-1070.2023.0170

所属专题： ICTC 2023(集成电路测试大会)

• ICTC 2023(集成电路测试大会)专题 • 下一篇

芯粒测试技术综述

解维坤^1,2,蔡志匡³,刘小婷³,陈龙²,张凯虹⁴,王厚军¹

1.电子科技大学自动化学院，成都　610097；2. 中国电子科技集团公司第五十八研究所，江苏无锡　214035；3. 南京邮电大学集成电路科学与工程学院，南京　210003；4. 无锡中微腾芯电子有限公司，江苏无锡　214000

收稿日期:2023-09-06 出版日期:2023-11-28 发布日期:2023-11-28
作者简介:解维坤（1980—），男，山东青岛人，博士研究生，高级工程师，主要研究方向为FPGA等可编程器件测试及芯粒可测性设计技术。

Overview of Chiplet Testing Technology

XIE Weikun¹^,2, CAI Zhikuang³, LIU Xiaoting³, CHEN Long², ZHANG Kaihong⁴, WANG Houjun¹

1. School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu 610097, China; 2.China ElectronicsTechnology Group Corporation No.58 ResearchInstitute, Wuxi 214035, China; 3.School of Integrated Circuit Science and Engineering,Nanjing University of Posts andTelecommunications, Nanjing210003, China; 4.Wuxi Zhongwei Tengxin Electronics Co., Ltd., Wuxi 214000, China

Received:2023-09-06 Online:2023-11-28 Published:2023-11-28

摘要/Abstract

摘要： 随着半导体工艺的发展，芯片工艺提升愈发困难，摩尔定律日趋放缓，而芯粒集成技术促进了多芯片封装的发展，有效地延续了摩尔定律。以2.5D、3D集成为主的芯粒异构集成芯片的测试方法与传统2D芯片测试有所不同，带来一些新的测试挑战。从当前芯粒测试的挑战分析入手，介绍了芯粒互连标准、互连测试和基于不同测试访问标准的可测性设计（DFT）方法，着重阐述各方法的优缺点以及相互之间的联系与区别，旨在帮助读者对芯粒测试技术进行系统性了解。

关键词: 芯粒, 可测性设计, TSV, 互连测试, 先进封装

Abstract: With the development of semiconductor process, chip process upgrading is more and more difficult, and Moore's law is slowing down. Chiplet integration technology has promoted the development of multichip packaging, effectively continuing Moore's law. The testing methods of Chiplet heterogeneous integrated chips, which are mainly based on 2.5D and 3D integration, are different from traditional 2D chip testing, bringing some new testing challenges.Starting with the analysis of the challenges of current Chiplet testing, Chiplet interconnection standards, interconnection testing and design for testability (DFT) methods based on different testing access standards are introduced, focusing on the advantages and disadvantages of each method as well as the connections and differences among them, aiming to help readers gain a systematic understanding of Chiplet testing technology.

Key words: Chiplet, design for testability, TSV, interconnection testing, advanced packaging

中图分类号:

TN407

解维坤, 蔡志匡, 刘小婷, 陈龙, 张凯虹, 王厚军. 芯粒测试技术综述[J]. 电子与封装, 2023, 23(11): 110101 .

XIE Weikun, CAI Zhikuang, LIU Xiaoting, CHENLong, ZHANG Kaihong, WANG Houjun. Overview of Chiplet Testing Technology[J]. Electronics & Packaging, 2023, 23(11): 110101 .

参考文献

[1] 马力, 项敏, 石磊, 等. 高端性能封装技术的某些特点与挑战[J]. 电子与封装, 2023, 23(3): 030109.
[2] 钟毅, 江小帆, 喻甜, 等. 芯片三维互连技术及异质集成研究进展[J]. 电子与封装, 2023, 23(3): 030102.
[3] 沈丹丹. 先进封装中凸点技术的研究进展[J]. 电子与封装, 2023, 23(6): 060208.
[4] UCI-Express. Universal Chiplet interconnect express (UCIe) specification Rev 1.0[EP/OL]. (2022-02-24 )[2023-11-09]. https://www.uciexpress.org/ucie-1-0-white-paper-download.
[5] 中国电子工业标准化技术协会. 小芯片接口总线技术要求: T/CESA 1248—2023 [S]. 北京: 中国电子工业标准化技术协会, 2023.
[6] 中国 Chiplet 产业联盟. 芯粒互联接口标准[EP/OL]. [2023-11-09]. http://www.iiisct.com/smart/upload/CMS1/202303/ACC1.0.pdf.
[7] 李晨光. Chiplet，迈出重要一步！[EP/OL].(2023-06-02 )[2023-11-09]. https://mp.weixin.qq.com/s/t5f7K74xU6_ifvhVJ8-KOg.
[8] 陈俊一. 中国Chiplet标准，能否给中国芯片蹚出新路？[EB/OL].(2023-01-18)[2023-11-09]. https://mp.weixin.qq.com/s/cJKRirbSc37WmW4EOTTF9Q.
[9] 秦贺. 基于JTAG测试技术的SiP测试技术研究[D]. 北京: 中国航天科技集团公司第一研究院, 2018: 11-12.
[10] HUANG L R, HUANG S Y, SUNTER S, et al. Oscillation-based prebond TSV test[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(9): 1440-1444.
[11] Test Technology Standards Committee. Test access port and boundary-scan architecture: IEEE 1149.1-2013 [S]. New York: IEEE, 2013.
[12] HUTNER M, SETHURAM R, VINNAKOTA B, et al. Special session: Test challenges in a chiplet marketplace[C]// 2020 IEEE 38th VLSI Test Symposium, April 5-8, 2020, San Diego, CA, USA. New York: IEEE, 2020: 19672241.
[13] IEEE Computer Society. Testability method for embedded core-based integrated circuits: IEEE 1500-2005[S]. New York: IEEE, 2005.
[14] IEEE Standards Association. Access and control of instrumentation embedded within a semiconductor device: IEEE 1687-2014[S]. New York: IEEE, 2014.
[15] IEEE Computer Society. Test access architecture for three-dimensional stacked integrated circuits: IEEE 1838-2019 [S]. New York: IEEE, 2020.
[16] MARINISSEN E J, CHI C C, VERBREE J, et al. 3D DfT architecture for pre-bond and post-bond testing[C]// 2010 IEEE International 3D Systems Integration Conference, Nov 16-18, 2010, Munich, Germany. New York: IEEE, 2010: 1-8.
[17] FKIH Y, VIVET P, ROUZEYRE B, et al. A JTAG based 3D DfT architecture using automatic die detection[C]//Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics, 24-27 June, 2013, Villach, Austria. New York: IEEE, 2013: 341-344.
[18] FKIH Y, VIVET P, ROUZEYRE B, et al. 2D to 3D test pattern retargeting using IEEE P1687 based 3D DFT architectures[C]// 2014 IEEE Computer Society Annual Symposium on VLSI, July 9-11, 2014, Tampa, FL, USA. New York: IEEE, 2014: 386-391.
[19] DURUPT J, VIVET P, SCHLOEFFEL J. IJTAG supported 3D DFT using Chiplet-footprints for testing multi-chips active interposer system[C]//2016 21th IEEE European Test Symposium, May 23-27, 2016, Amsterdam, Netherlands. New York: IEEE, 2016: 1-6.
[20] YE J C, KOCHTE M A, LEE K J, et al. Autonomous testing for 3D-ICs with IEEE std. 1687[C]// 2016 IEEE 25th Asian Test Symposium, Nov 21-24, 2016, Hiroshima, Japan. New York: IEEE, 2016: 215-220.
[21] CUI C M, HUANG J L. A 3DIC interconnect interface test and repair scheme based on Hybrid IEEE1838 die wrapper register and BIST circuit[C]// 2021 IEEE European Test Symposium (ETS), May 24-28, 2021, Bruges, Belgium. New York: IEEE, 2021: 1-2.

中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

芯粒测试技术综述

Overview of Chiplet Testing Technology

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 15

编辑推荐

Metrics

本文评价

[1]	刘冠东;王伟豪;万智泉;段元星;张坤;李洁;戚定定;王传智;李顺斌;邓庆文;张汝云. 晶上系统:设计、集成及应用[J]. 电子与封装, 2024, 24(8): 80201-.
[2]	张旋,李海娟,吴道伟,张雷. 2.5D TSV转接板无损检测方法的研究[J]. 电子与封装, 2024, 24(6): 60102-.
[3]	许增光, 李哲, 钟诚, 刘志权. TSV电镀过程中Cu生长机理的数值模拟研究进展^*[J]. 电子与封装, 2024, 24(6): 60104-.
[4]	王成迁,汤文学,戴飞虎,丁荣峥,于大全. 面向大算力应用的芯粒集成技术[J]. 电子与封装, 2024, 24(6): 60105-.
[5]	徐成,樊嘉祺,张宏伟,王华,陈天放,刘丰满. 硅转接板制造与集成技术综述[J]. 电子与封装, 2024, 24(6): 60106-.
[6]	范泽域, 王方成, 刘强, 黄明起, 叶振文, 张国平, 孙蓉. 三维集成电路先进封装中聚合物基材料的研究进展^*[J]. 电子与封装, 2024, 24(6): 60107-.
[7]	何慧敏, 廖成意, 刘丰满, 戴风伟, 曹睿. 集成硅基转接板的PDN供电分析[J]. 电子与封装, 2024, 24(6): 60108-.
[8]	马书英, 付东之, 刘轶, 仲晓羽, 赵艳娇, 陈富军, 段光雄, 边智芸. 硅通孔三维互连与集成技术[J]. 电子与封装, 2024, 24(6): 60109-.
[9]	张爱兵, 李洋, 姚昕, 李轶楠, 梁梦楠. 基于硅通孔互连的芯粒集成技术研究进展[J]. 电子与封装, 2024, 24(6): 60110-.
[10]	黎科,张鑫硕,夏启飞,钟毅,于大全. 集成电路互连微纳米尺度硅通孔技术进展^*[J]. 电子与封装, 2024, 24(6): 60111-.
[11]	戚晓芸,马岩,杜玉,王晨曦. 无凸点混合键合三维集成技术研究进展^*[J]. 电子与封装, 2024, 24(6): 60114-.
[12]	汤文学,孙莹,周立彦. Chiplet封装用有机基板的信号完整性设计[J]. 电子与封装, 2024, 24(2): 20101-.
[13]	田文超;谢昊伦;陈源明;赵静榕;张国光. 人工智能芯片先进封装技术[J]. 电子与封装, 2024, 24(1): 10204-.
[14]	曹振吉, 曹杨, 隽扬, 曹靓, 马金龙. 反熔丝FPGA可配置I/O端口可测性设计研究[J]. 电子与封装, 2023, 23(8): 80304-.
[15]	沈丹丹. 先进封装中凸点技术的研究进展[J]. 电子与封装, 2023, 23(6): 60208-.