关键词: 锁相环, 小数分频, 计数器

Abstract: A method based on phase-locked loop (PLL) multi-phase clock is proposed. It is introduced to realize fractional frequency division. A configurable counting step phase selection counter is used for cyclic counting. The value of the counter controlles selection signal of the phase selector. The phase selector’s input is multiple phase versions of the PLL output clock. The output is both the counting clock of phase selection counter and the input clock of the integer frequency divider. The phase selector’s output clock phase changes as the counter accumulates in cycles. So the input clock of the integer frequency divider is constantly inserted a phase difference, and its output realizes the resolution of 0.125 fractional frequency divider. The results are verified by simulation.

Key words: phase-locked loop, fractional frequency divider, counter